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參數(shù)資料
| 型號： | SC16C550BIBS,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 15/48頁 |
| 文件大小： | 0K |
| 描述： | IC UART SINGLE W/FIFO 32-HVQFN |
| 標準包裝： | 490 |
| 特點： | 可編程 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-HVQFN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 568-3263 935279497151 SC16C550BIBS-S |
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SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
22 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C550B provides four levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 13 “Interrupt source” shows the data values (bits 3:0) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 12.
RX trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes)
001
014
108
1114
Table 13.
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
2
1
0
RXRDY (Receive Data time-out)
3
0
1
0
TXRDY (Transmitter Holding Register Empty)
4
0
MSR (Modem Status Register)
Table 14.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
5:4
ISR[5:4]
not used
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).
logic 0 or cleared = default condition
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C550BIBS-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIBS-S | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550BIN40 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 DIP40 |
| SC16C550BIN40,112 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C550IA44 | 制造商:NXP Semiconductors 功能描述:UART 16BYTE FIFO 16C550 PLCC44 |
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