參數(shù)資料
型號: SAK-XC888CLM-8FFA
廠商: INFINEON TECHNOLOGIES AG
元件分類: 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù): 37/119頁
文件大小: 895K
代理商: SAK-XC888CLM-8FFA
XC886/888CLM
Functional Description
Data Sheet
Prelimary
33
V0.1, 2006-02
91
H
P1_DIR
P1 Direction Register
Reset: 00
H
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
92
H
P5_DATA
P5 Data Register
Reset: 00
H
93
H
P5_DIR
P5 Direction Register
Reset: 00
H
A0
H
P2_DATA
P2 Data Register
Reset: 00
H
A1
H
P2_DIR
P2 Direction Register
Reset: 00
H
B0
H
P3_DATA
P3 Data Register
Reset: 00
H
B1
H
P3_DIR
P3 Direction Register
Reset: 00
H
C8
H
P4_DATA
P4 Data Register
Reset: 00
H
C9
H
P4_DIR
P4 Direction Register
Reset: 00
H
RMAP = 0, Page 1
80
H
P0_PUDSEL
P0 Pull-Up/Pull-Down Select Register
Reset: FF
H
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
P0
rw
86
H
P0_PUDEN
P0 Pull-Up/Pull-Down Enable Register
Reset: C4
H
90
H
P1_PUDSEL
P1 Pull-Up/Pull-Down Select Register
Reset: FF
H
91
H
P1_PUDEN
P1 Pull-Up/Pull-Down Enable Register
Reset: FF
H
92
H
P5_PUDSEL
P5 Pull-Up/Pull-Down Select Register
Reset: FF
H
93
H
P5_PUDEN
P5 Pull-Up/Pull-Down Enable Register
Reset: FF
H
A0
H
P2_PUDSEL
P2 Pull-Up/Pull-Down Select Register
Reset: FF
H
A1
H
P2_PUDEN
P2 Pull-Up/Pull-Down Enable Register
Reset: 00
H
B0
H
P3_PUDSEL
P3 Pull-Up/Pull-Down Select Register
Reset: BF
H
B1
H
P3_PUDEN
P3 Pull-Up/Pull-Down Enable Register
Reset: 40
H
C8
H
P4_PUDSEL
P4 Pull-Up/Pull-Down Select Register
Reset: FF
H
C9
H
P4_PUDEN
P4 Pull-Up/Pull-Down Enable Register
Reset: 04
H
RMAP = 0, Page 2
80
H
P0_ALTSEL0
P0 Alternate Select 0 Register
Reset: 00
H
Bit Field
Type
Bit Field
Type
Bit Field
Type
P7
rw
P7
rw
P7
rw
P6
rw
P6
rw
P6
rw
P5
rw
P5
rw
P5
rw
P4
rw
P4
rw
P4
rw
P3
rw
P3
rw
P3
rw
P2
rw
P2
rw
P2
rw
P1
rw
P1
rw
P1
rw
P0
rw
P0
rw
P0
rw
86
H
P0_ALTSEL1
P0 Alternate Select 1 Register
Reset: 00
H
90
H
P1_ALTSEL0
P1 Alternate Select 0 Register
Reset: 00
H
Table 10
Addr
Port Register Overview
(cont’d)
Register Name
Bit
7
6
5
4
3
2
1
0
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