參數(shù)資料
型號: SAB83C517A-5N18-T3
文件頁數(shù): 44/77頁
文件大?。?/td> 1358K
代理商: SAB83C517A-5N18-T3
SAB 80C517A/83C517A-5
Semiconductor Group
43
1994-05-01
Interrupt Structure
The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request
flags.
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt
request is more than 3 machine cycles and less than 9 machine cycles.
External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 2 to 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.
For programming of the priority levels the interrupt vectors are combined to pairs or triples.
Each pair or triple can be programmed individually to one of four priority levels by setting or
clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt
request sources, the enabling and the priority level structure.
Table 5
Interrupt Sources and Vectors
Interrupt Request Flags
Interrupt Vector Address
Interrupt Source
IE0
TF0
IE1
TF1
RI0 + TI0
TF2 + EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
RI1/TI1
ICMP0 to ICMP7
CTF
ICS
ICR
0003
H
000B
H
0013
H
001B
H
0023
H
002B
H
0043
H
004B
H
0053
H
005B
H
0063
H
006B
H
0083
H
0093
H
009B
H
00A3
H
00AB
H
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
Serial channel 0
Timer 2 overflow/ext. reload
A/D converter
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Serial channel 1
Compare match interrupt of
Compare Registers CM0-
CM7 assigned to Timer 2
Compare timer overflow
Compare match interrupt of
Compare Register COMSET
Compare match interrupt of
Compare Register COMCLR
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