參數(shù)資料
型號(hào)： SAB82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 43/126頁
文件大?。?/td> 730K
代理商： SAB82526N
Semiconductor Group
43
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Table 4
Special Condition Interrupts
SPECIAL CONDITION INTERRUPTS
Layer 2-Specific *
Activated only if the "Auto" operating mode has been selected
via MODE register)
RSC
Receive Status Change
Activated after a status change of the opposite
stations receiver has been detected (Receiver
Ready/Receiver Not Ready) due to the
reception of a
– RR frame, if receiver was not ready, or
– RNR frame, if receiver was ready.
PCE
Protocol Error
Activated if a protocol violation has been
detected due to the reception of
– an S-, or
I
-frame with incorrect N(R),
– an S-frame containing an I-field.
Internal Timer
TIN
Timer Interrupt
(ISTA)
Activated if the internal timer and repeat
counter has been expired (see description of
TIMR register in
chapter 8).
External Pin
CSC
CTS Status Change
(EXIR)
* Only activated if enabled by setting the CIE
bit in the CCR2 register.
4.4 DMA Interface
The HSCX comprises a 4-channel DMA interface for fast and effective data transfers.
For both serial channels, a separate DMA Request Output for Transmit (DRQT) and receive
direction (DRQR) as well as a DMA Acknowledgement (DACK) input is provided.
The HSCX activates the DRQ line as long as data transfers are needed from/to the specific
FIFO (level triggered demand transfer mode of DMA controller).
It’s the responsibility of the DMA controller to perform the correct amount of bus cycles. Either
read cycles will be performed if the DMA transfer has been requested from the receiver, or write
cycles if DMA has been requested from the transmitter. If the DMA controller provides a DMA
acknowledge signal (input to the HSCX’s DACK pin), each bus cycle implicitly selects the top
of the specific FIFO and neither address (via A0-A6) nor chip select need to be supplied (
I
/O
to Memory transfers). If no DACK signal is supplied, normal read/write operations (providing
addresses) must be performed (memory to memory transfers).
The HSCX deactivates the DRQ line immediately after the last read/write cycle of the data
transfer has started.
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