參數(shù)資料
型號： SAB82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 100/126頁
文件大?。?/td> 730K
代理商： SAB82526N
Semiconductor Group
100
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Channel Configuration Register 2 (READ/WRITE)
Value after RESET: 00
H
The meaning of the individual bits in CCR2 depends on the selected clock mode via
CCR 1 as follows:
CCR2
clock mode 0,1
SOC1
SOC0
(2C/6C)
0
0
0
CIE
RIE
DIV
clock mode 2,6
BR9
BR8
BDF
TSS
TIO
CIE
RIE
DIV
clock mode 3,7
BR9
BR8
BDF
0
TIO
CIE
RIE
DIV
clock mode 5
SOC1
SOC0
XCS0
RCS0
TIO
CIE
RIE
DIV
clock mode 4
SOC1
SOC0
0
0
TIO
CIE
RIE
DIV
In a bus configuration (selected via CCR1) the function of pin RTS can be defined
00 … RTS output is activated during the transmission of a frame.
10 … RTS output is always high (RTS disabled).
11 … RTS indicates the reception of a data frame (active low).
In point-to-point configuration (selected via CCR1) the T
×
D and R
×
D pins may be flipped
0X … data is transmitted on T
×
D, received on R
×
D pin (normal case)
1X … data is transmitted on R
×
D, received on T
×
D pin
SOC1, SOC0 … Special Output Control
BR9, BR8 … Baudrate, Bit 9-8 (higher significant bits, refer to description of BGR
register).
0 … The division factor of the baudrate generator is set to 1 (constant).
1 … The division factor is adjusted with BR9 – BR0 bits of CCR2 and BRG register.
BDF … Baudrate Division Factor
0 … The transmit clock is input to the T
×
CLKA/T
×
CLKB pins.
1 … The transmit clock is derived from the baudrate generators output divided by 16.
TSS … Transmit Clock Source Select
0 … T
×
CLKA, T
×
CLKB pins are inputs
1 … T
×
CLKA, T
×
CLKB pins are outputs
TIO … Transmit Clock Input Output Switch
相關(guān)PDF資料
PDF描述
SAF82525N Data Communications ICs
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SAF82526N Data Communications ICs
SAB82525 Data Communications ICs
SAB82525H Data Communications ICs
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參數(shù)描述
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