參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 64/126頁
文件大?。?/td> 730K
代理商: SAB82525N
Semiconductor Group
42
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Table 3
Transmit Interrupts
TRANSMIT INTERRUPTS
XPR
Transmit Pool Ready
(ISTA)
Activated whenever a 32-byte FIFO pool is
empty and accessible to the CPU, i.e.
– following a XRES command via CMDR.
Interrupt Mode:
Repeatedly during frame transmission started
by XTF or XIF command, and no end of
message indication (XME command) has
been issued yet by the CPU,
– after the end-of-message indication
when frame transmission of a transparent
frame is completed (i.e. CRC and closing flag
sequence are shifted out),
Auto-Mode:
If
an
I-frame
has
been
positively
acknowledged by the opposite station.
XMR
Transmit Message Repeat
(EXIR)
Auto-Mode:
Activated if the last transmitted I-frame has to
be repeated due to the reception of a negative
acknowledgement
(S-,
or
I-frame
with
unaccording receive sequence number) of the
opposite station.
Bus Configuration:
A collision has occurred after sending the
32nd data byte of a message.
Point-to-Point Configuration:
CTS has been withdrawn after sending the
32nd data byte.
XDU
Transmit Data Underrun
(EXIR)
Activated if the XFIFO holds no further data,
i.e. all data has been shifted out via the serial
T
×D pin, but no End Of Message (EOM)
indication has been detected by the HSCX.
The EOM indication is supplied either
– by a XME command from the CPU in
Interrupt Mode,
– or by checking the pre-programmed
transmit byte count (via XBCH, XBCL) against
the actual amount of data bytes shifted out in
DMA Mode.
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