參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 13/126頁
文件大?。?/td> 730K
代理商: SAB82525N
Semiconductor Group
11
82525
82526
82525
82526
SAB
SAF
Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Output (O)
Function
9
16
RXDA
RXDB
I
Receive Data (channel A/channel B)
Serial data is received on these pins at standard TTL or
CMOS levels.
10
15
O
11
14
I
Clear to Send (channel A/channel B)
A low on the CTS inputs enables the respective transmitter.
Additionally, an interrupt may be issued if a state transition
occurs at the CTS pin (programmable feature). If no "Clear
To Send" function is required, the CTS inputs can be
connected directly to VSS.
Collision Data (channel A/channel B)
In a bus configuration, the external serial bus must be
connected to the respective C
× D pin for collision
detection.
12
13
TXDA
TXDB
O
Transmit Data (channel A/channel B)
Transmit data is shifted out via these pins at standard TTL
or CMOS levels. These pins can be programmed to work
either as push-pull, or open drain outputs supporting bus
configurations.
17
RES
I
RESET
A high signal on this input forces the HSCX into the reset
state. The HSCX is in power-up mode during reset and in
power-down mode after reset. The minimum pulse width is
1.8
s.
Request to Send (channel A/channel B)
When the RTS bit in the mode register is set, the RTS
signal goes low. When the RTS is reset, the signal goes
high if the transmitter has finished and there is no further
request for a transmission.
In a bus configuration, this pin can be programmed via
CCR2 to:
stay always high (RTS disabled).
go low during the actual transmission of a frame shifted
by one clock period, excluding collision bits
go low during the reception of a data frame
RTSA
RTSB
CTSA/
CXDA
CTSB/
CXDB
14
21
15
20
16
19
17
18
22
P-LCC P-MQFP
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參數(shù)描述
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