參數(shù)資料
型號(hào)： SAB-C513AO
廠商： INFINEON TECHNOLOGIES AG
元件分類： 8位微控制器
英文描述： 8-bit CMOS Microcontroller
中文描述： 8位CMOS微控制器
文件頁(yè)數(shù)： 36/59頁(yè)
文件大?。?/td> 1634K
代理商： SAB-C513AO
C513AO
Data Sheet
34
02.00
Power Saving Modes
The C513AO provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Power-
down Mode.
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are
able to function. Idle mode is entered by software and can be left by an interrupt or reset.
Slow down mode
The controller keeps up the full operating functionality, but its normal clock frequency is internally
divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32nd
of their normal operating frequency and also reduces power consumption.
Power down mode
The operation of the C513AO is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. This power down
mode is entered by software and can be left by reset or a short low pulse at pin P3.2/INT0.
In the power down mode of operation,
V
can be reduced to minimize power consumption. It must
be ensured, however, that
V
DD
is not reduced before the power down mode is invoked, and that
V
DD
is restored to its normal operating level, before the power down mode is terminated.
Table 10
gives
a general overview of the entry and exit procedures of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering
Example
ORL PCON, #01
H
Leaving by
Remarks
Idle mode
Occurrence of an any
enabled interrupt
Hardware reset
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with clock
Internal clock rate is reduced to
1/32 of its nominal frequency
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/32
of its nominal frequency
Slow Down Mode
In normal mode:
ORL PCON,#10
H
With idle mode:
ORL PCON,#11
H
ANL PCON,#0EF
H
or Hardware reset
Occurrence of any
enabled interrupt and
the instruction
ANL PCON,#0EF
H
Hardware reset
Hardware reset
Short low pulse at pin
P3.2/INT0
Power Down
Mode
ORL PCON, #02
H
Oscillator is stopped;
contents of on-chip RAM and
SFRs are maintained;
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