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參數(shù)資料
| 型號(hào)： | SAB-C513AO |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 1634K |
| 代理商： | SAB-C513AO |
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C513AO
Data Sheet
28
02.00
SSC Interface
The Synchronous Serial Channel (SSC) interface is compatible to the popular SPI serial bus
interface. It can be used for simple I/O expansion via shift registers, for connection with a variety of
peripheral components (such as A/D converters, EEPROMs etc.), or interconnection of several
microcontrollers in a master/slave structure. The SSC unit supports full-duplex or half-duplex
operation and can run in Master Mode or Slave Mode.
Figure 15
shows the block diagram of the SSC.
Figure 15
SSC Block Diagram
Interrupt System
The C513AO provides seven interrupt sources with two priority levels. Five of the interrupts can be
generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, USART, and SSC) and three of the
interrupts may be triggered externally (P1.1/T2EX, P3.2/INT0, P3.3/INT1). A non-maskable eighth
interrupt is reserved for external wake-up from power-down mode.
Figure 16
gives a general overview of the interrupt sources and illustrates the request and the
control flags.
Table 8
lists the vector addresses of each interrupt source.
MCB02735
P1.2/SCLK
P1.3/SRI
P1.4/STO
P1.5/SLS
Pin
Control
Logic
Shift Register
Receive Buffer Register
STB
Clock Selection
Clock Divider
SRB
f
OSC
Control Register
Status Register
Int. Enable Reg.
SCIEN
SSCCON
SCF
Control Logic
Internal Bus
Interrupt
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