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參數(shù)資料
| 型號(hào)： | SAB-C504-L40M |
| 廠商： | SIEMENS A G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8-BIT, 40 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 31/49頁 |
| 文件大?。?/td> | 962K |
| 代理商： | SAB-C504-L40M |
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Semiconductor Group
31
C504
Fail Save Mechanisms
The C504 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure.
– 15-bit reloadable watchdog timer
– Oscillator Watchdog
Watchdog Timer
The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either
f
SOC
/
12 or
f
CYCLE
/32. From the 15-bit watchdog timer count value only the upper 7 bits can be
programmed.
Figure 5
shows the block diagram of the programmable watchdog timer.
Figure 13
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be
stopped during active mode of the device. If the software fails to refresh the running watchdog timer
an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog)
can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer
is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction
sequence has been implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and power down
mode of the processor. Therefore, it is possible to use the idle mode in combination with the
watchdog timer function.
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