參數(shù)資料
型號(hào)： SAB-C165-R25M
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 14 MHz, MICROCONTROLLER, PQFP100
封裝： EIAJ, MQFP-100
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 306K
代理商： SAB-C165-R25M
11Jul97@13:32h Intermediate Version
Semiconductor Group
10
C165 / 3 V
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
The following notes apply to the next two timing tables
(Multiplexed Bus and Demultiplexed Bus):
1) RW-delay and t
A refer to the next following bus cycle.
2) Read data are latched with the same clock edge that triggers the address change and the rising
RD edge. Therefore address changes before the end of RD have no impact on read cycles.
*) The rising edges of CS represent the worst case. The delay for falling edges is lower.
AC Characteristics
Multiplexed Bus
V
CC = 2.7 V to 3.6 V; VSS = 0 V
TA = 0 to +70 °C
for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F
T
A = -40 to +85 °C
for SAF-C165-L25M
C
L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2
t
A + tC + tF (214.3/250 ns at 14/12 MHz CPU clock without waitstates)
Description
Symbol Values
ALE Extension
t
A
TCL * <ALECTL> 1)
Memory Cycle Time Waitstates
tC
2TCL * (15 - <MCTC>)
Memory Tristate Time
t
F
2TCL * (1 - <MTTC>)
Parameter
Symbol
Max. CPU Clock
= 14 MHz
(0 to 70 °C)
Variable CPU Clock
1/2TCL=1..14 MHz, 0..70 °C
1/2TCL=1..12 MHz, -40..85°C
Unit
min.
max.
min.
max.
ALE high time
t
5
CC 16 +
t
A
–
TCL - 20
+
t
A
–ns
Address setup to ALE
t
6
CC 6 + t
A
–
TCL - 30
+
tA
–ns
Address hold after ALE
t7
CC 26 + t
A
–
TCL - 10
+
tA
–ns
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