參數(shù)資料
型號: SAA8116ET
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital PC-camera signal processor including microcontroller and USB interface
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA112
封裝: 7 X 7 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT-630-1, TFBGA-112
文件頁數(shù): 44/60頁
文件大?。?/td> 237K
代理商: SAA8116ET
2001 May 04
44
Philips Semiconductors
Product specification
Digital PC-camera signal processor including
microcontroller and USB interface
SAA8116
Table 50
Register SET_ADDRESS (address: 0xD0H)
Detailed description of the write (1 byte) following command 0xD0H
Table 51
Register SET_EP_ENABLE (address: 0xD8H)
Detailed description of the write (1 byte) following command 0xD8H
Table 52
Register GETSET_MODE (address: 0xF3H)
Detailed description of the write (one byte) following command 0xF3H; notes 1, 2 and 3
Notes
1.
2.
GETSET_MODE command can write from 1 to 4 consecutive bytes. The detailed description above concerns byte 0.
GETSET_MODE bytes 1 and 2 are used to set the size of the isochronous video packets. Byte 1 corresponds to the
LSB to define the packet size. Bits 0 and 1 of byte 2 set the 2 MSBs. By default, the two bytes are forced to 0.
GETSET_MODE byte 3 sets the FIFO offset.
3.
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
ENABLE_ADD: enable the function (by default = 0)
DEVICE_address: set the USB assigned address (by default = 0)
X
X
X
X
X
X
X
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
reserved
ENABLE_EP: enable end-point
Non-control end-points are disabled (by default)
Non-control end-points are enabled
0
10
BIT
PARAMETER
7
6
5
4
3
2
1
0
X
X
X
X
X
reserved
FIFO_ACTIVE: set the video FIFO status
FIFO is inactive; only zero-length packet are sent upstream
functional mode (by default)
ALWAYS_PLLCLOCK: control internal clock signals
clocks and PLL are stopped whenever not needed (e.g. suspend mode)
clocks and PLL are always running even in suspend mode (by default)
INTERRUPT_ONNAK: control transaction reporting
only successful transactions are reported
NAK is reported and generates an interrupt (by default)
0
1
0
1
0
1
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