參數(shù)資料
型號(hào)： SAA7712
廠商： NXP Semiconductors N.V.
英文描述： Sound effects DSP
中文描述： DSP的音效
文件頁(yè)數(shù)： 25/44頁(yè)
文件大?。?/td> 178K
代理商： SAA7712
1999 Aug 05
25
Philips Semiconductors
Preliminary specification
Sound effects DSP
SAA7712H
8.9
Power supply connection and EMC
The digital part of the chip has in total 5 positive supply line
connections and 8 ground connections. To minimise
radiationthechipshouldbeputonadoublelayerPCBwith
a large ground plane on one side. The ground supply lines
should have a short connection to this ground plane. A coil
and capacitor network in the positive supply line can be
used as high frequency filter.
8.10
Test mode connections
Pins TSCAN, RTCB and SHTCB are used to put the chip
in test mode and to test the internal connections. Each pin
has an internal pull-down resistor to ground. In the
applicationthesepinscanbeleftopen-circuitorconnected
to ground.
9
I
2
C-BUS FORMAT
9.1
Addressing
Before any data is transmitted on the I
2
C-bus, the device
whichshouldrespondisaddressedfirst.Theaddressingis
alwaysdonewiththefirstbytetransmittedaftertheSTART
procedure.
9.2
Slave address (pin A0)
The SAA7712H acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The slave address is shown in Table 7.
Table 7
Slave address
The subaddress bit A0 corresponds to the hardware
address pin A0 which allows the device to have two
addresses. This allows the control of two SAA7712Hs via
the same I
2
C-bus.
MSB
LSB
0
0
1
1
1
1
A0
R/W
9.3
Write cycles
The I
2
C-bus configuration for a write cycle is shown in
Fig.15. The write cycle is used to write the bytes to control
the PLL for the DSP clock generation, the format of the
I
2
S-bus and some other settings. More details can be
found in the I
2
C-bus memory map (see Table 8).
The data length is 2 or 3 bytes, depending on the
accessed memory. The slave receiver detects the address
and adjusts the number of bytes accordingly. For XRAM,
the data word length is 18 bits and 3 bytes are sent over
the I
2
C-bus. The upper 6 bits (i.e. bit 7 to bit 2) of the first
byte DATA H are don’t care. For YRAM, the data word
lengthis12 bitsand2 bytesaresentovertheI
2
C-bus.The
leftnibble(i.e.bit 7 tobit 4)ofthefirstbyteDATA Hisdon’t
care.
9.4
Read cycles
The I
2
C-bus configuration for a read cycle is shown in
Fig.16. The read cycle is used to read the data values from
XRAM or YRAM. The master starts with a START
condition (S), the SAA7712H address ‘0011110’ and a
logic 0 (write) for the read/write bit. This is followed by an
acknowledge of the SAA7712H. The master then writes
the memory high address and memory low address where
the reading of the memory content of the SAA7712H must
start. The SAA7712H acknowledges these addresses
both.
The master than generates a repeated START and again
the SAA7712H address ‘0011110’ but this time followed
by a logic 1 (read) of the read/write bit. From this moment
on, the SAA7712H will send the memory content in groups
of 2 (YRAM) or 3 (XRAM) bytes to the I
2
C-bus, each time
acknowledged by the master. The master stops this cycle
by generating a negative acknowledge, then the
SAA7712H frees the I
2
C-bus and the master can generate
a STOP condition (P).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7712H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sound effects DSP
SAA7715 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Signal Processor
SAA7715H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Signal Processor
SAA7724H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car radio digital signal processor
SAA7740 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Audio Processing IC DAPIC
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