參數(shù)資料
型號(hào): SAA7707H
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號(hào)處理
英文描述: Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W
中文描述: 0-BIT, 36.86 MHz, OTHER DSP, PQFP80
封裝: 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-318-2, QFP-80
文件頁數(shù): 14/48頁
文件大小: 244K
代理商: SAA7707H
1997 May 30
14
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
8.12
TAPE/AUX de-multiplex
The auxiliary and tape inputs also use the stereo decoder.
Because of this, the left and right channels are multiplexed
with a 38 kHz square wave to obtain a signal similar to the
FM multiplexed signal. Auxiliary inputs can be e.g.
TV-sound, remote players (tape deck, CD-changer with
analog output etc.). The signal-to-noise ratio from such
sources is limited by the ADC in the SAA7707H (>75 dB).
The decimation filter of the ADC attenuates the harmonic
signals from this stereo encoder. For an optimum channel
separation, the 38 kHz switch signal has to be phase
corrected to compensate for the delay of the ADC and
decimation filters. This can be adjusted with the 3-bit group
delay compensation in the IAC control register. Signal
frequencies above 19 kHz at the input of the multiplexer
are converted to the audio base-band and are therefore
not allowed.
8.13
Signal-to-noise considerations
Due to the pre-emphasis of FM broadcasts, the theoretical
signal-to-noise ratio is approximately 3 dB higher for FM
stereo in comparison with multiplexed inputs.
To avoid aliasing into the tape channel, the tape noise from
the pre-amplifier must be attenuated before
analog-to-digital conversion with a 1st-order 10 kHz
low-pass filter. The frequency response is equalized after
the stereo decoder in the DSP program before the Dolby
decoder software. Using this filter, the signal-to-noise ratio
of this channel is degraded by 3 dB. This results in a
signal-to-noise ratio that is overall 6 dB lower than a tape
input with respect to FM stereo.
8.14
Channel separation correction
The channel separation is approximately 50 dB at 1 kHz
and 35 dB at 15 kHz. Because the frequency response of
the ADC has some deviation from the flat curve around
38 kHz, a perfect channel separation cannot be obtained.
Therefore, the de-multiplexed signal is corrected for
crosstalk in the DSP program.
8.15
Input selection switches
A schematic diagram of the input selection is illustrated in
Fig.5. The input selection is controlled by bits in the input
selector control register. The relationship between these
bits and the switches is indicated in Table 2.
Table 2
Analog input selection
8.16
Analog inputs supply
The analog input circuit has its own separate power supply
connections to allow maximum filtering. These pins are
V
SSA1
for the analog ground and V
DDA1
for the analog
power supply. V
SSG
is the connection to the guard ring
which isolates the analog part from the digital filters.
This pin has to be connected to the analog ground.
8.17
Digitally controlled sampling clock (DCS)
The crystal clock generates a continuous clock signal for
the internal DSP core. In the radio mode, the stereo
decoder, the RDS decoder, the ADCs and the level
decimation filters have to run synchronously with the
19 kHz pilot. Therefore, a clock signal with a controlled
frequency with a multiple of 19 kHz
(9.728 MHz = 512
×
19 kHz) is required.
In the SAA7707H, the patented method of a
non-continuous digitally controlled sampling clock has
been implemented. A frequency of 9.728 MHz is
generated by a special dividing mechanism of the master
crystal clock. Since the dividing mechanism is fixed, only a
crystal frequency of 36.86 MHz can be used.
The DCS system is controlled by up/down information
from the stereo decoder. For mono transmissions, the
DCS clock is still controlled by the stereo decoder loop.
The output keeps the DCS free-running at a multiple
frequency of 19 kHz
±
2 Hz. In TAPE/AUX and AM mode,
the DCS clock must always be put in preset mode by the
input selector control register.
I
2
C-BUS SELECTION
BIT
SWITCH
AM/FM
AUX/
RADIO
TAPE/
AUX
SFM
SAM SAUX SAUX
0
1
x
x
0
0
1
1
x
x
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
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