參數(shù)資料
型號: SAA7388
廠商: NXP Semiconductors N.V.
英文描述: Error correction and host interface IC for CD-ROM ELM
中文描述: 錯誤更正和主機接口集成電路的CD - ROM榆木
文件頁數(shù): 6/60頁
文件大小: 226K
代理商: SAA7388
1996 Apr 26
6
Philips Semiconductors
Preliminary specification
Error correction and host interface IC for
CD-ROM (ELM)
SAA7388
DGND4
CS1/HEN
HWR
HRD
DMACK
IORDY/WAIT/HFBLB
SCRST/STEN
41
42
43
44
45
46
47
I
I
I
I
O
O
digital ground 4
host interface enable input (active LOW)
host interface write enable input (active LOW)
host interface read enable input (active LOW)
DMA acknowledge input
host interface wait output (active LOW); 3-state control
host interface status enable output ATAPI sub-CPU reset signal
(active LOW)
ATAPI DMA request host interface data enable output (active LOW);
3-state control
host interface end of process flag output ATAPI host interrupt request
(active LOW); 3-state control
digital supply voltage 2 (5 V)
host interface data bus input/output line 0
host interface database input/output line 1
host interface database input/output line 2
host interface data bus input/output line 3
host interface data bus input/output line 4
host interface data bus input/output line 5
host interface data bus input/output line 6
host interface data bus input/output line 7
digital ground 5
host interface data bus input/output line 8
host interface data bus input/output line 9
host interface data bus input/output line 10
host interface data bus input/output line 11
host interface data bus input/output line 12
host interface data bus input/output line 13
host interface data bus input/output line 14
host interface data bus input/output line 15
digital ground 6
host interface data input (active LOW)/command select input host interface
address line 0
ATAPI address line input 1
ATAPI address line input 2
ATAPI chip select input 2
ATAPI 16-bit data select output
digital supply voltage 2 (5 V)
buffer RAM address bus output line 0
buffer RAM address bus output line 1
buffer RAM address bus output line 2
DMARQ/DTEN
48
O
IRQ/EOP/HFBC
49
O
V
DDD2
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
DGND5
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
DGND6
DA0/CMD
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DA1
DA2/EJECT
CS2/SELRQ
IOCS16
V
DDD2
RA0
RA1
RA2
70
71
72
73
74
75
76
77
I
I
I
O
O
O
O
SYMBOL
PIN
I/O
DESCRIPTION
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