參數資料
型號: SAA5551PS/NNNN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, PLASTIC, SDIP-52
文件頁數: 78/80頁
文件大?。?/td> 340K
代理商: SAA5551PS/NNNN
1999 Oct 27
8
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
6.2
Pin description
Table 1
SDIP52 and LQFP100 packages
SYMBOL
PIN
TYPE
DESCRIPTION
SDIP52
LQFP100
P2.0/TPWM
1
100
I/O
Port 2. 8-bit programmable bidirectional port with
alternative functions.
P2.0/TPWM is the output for the 14-bit high precision
PWM and P2.1/PWM0 to P2.7/PWM6 are the outputs
for the 6-bit PWMs 0 to 6.
P2.1/PWM0
2
93
I/O
P2.2/PWM1
3
94
I/O
P2.3/PWM2
4
95
I/O
P2.4/PWM3
5
96
I/O
P2.5/PWM4
6
97
I/O
P2.6/PWM5
7
98
I/O
P2.7/PWM6
8
1
I/O
P3.0/ADC0
9
2
I/O
Port 3. 8-bit programmable bidirectional port with
alternative functions.
P3.0/ADC0 to P3.3/ADC3 are the inputs for the
software ADC facility and P3.4/PWM7 is the output for
the 6-bit PWM7. P3.5 to P3.7 have no alternative
functions and are only available with the LQFP100
package.
P3.1/ADC1
10
4
I/O
P3.2/ADC2
11
5
I/O
P3.3/ADC3
12
6
I/O
P3.4/PWM7
30
44
I/O
P3.5
54
I/O
P3.6
59
I/O
P3.7
25
I/O
VSSC
13
11
core ground
P0.0
14
16
I/O
Port 0. 8-bit programmable bidirectional port.
P0.5 and P0.6 have 8 mA current sinking capability for
direct drive of LEDs.
P0.1
15
17
I/O
P0.2
16
18
I/O
P0.3
17
22
I/O
P0.4
18
24
I/O
P0.5
19
13
I/O
P0.6
20
28
I/O
P0.7
21
29
I/O
VSSA
22
30
analog ground
CVBS0
23
31
I
Composite video input. A positive-going 1 V
(peak-to-peak) input is required; connected via a
100 nF capacitor.
CVBS1
24
32
I
SYNC_FILTER
25
34
I
CVBS sync lter input. This pin should be connected to
VSSA via a 100 nF capacitor.
IREF
26
35
I
Reference current input for analog circuits, connected
to VSSA via a 24 k resistor.
FRAME
27
41
O
De-interlace output synchronized with the VSYNC
pulse to produce a non-interlaced display by
adjustment of the vertical deection circuits.
VPE
28
42
I
OTP programming voltage
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