參數(shù)資料
型號(hào): SAA5551PS/NNNN
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52
封裝: 0.600 INCH, PLASTIC, SDIP-52
文件頁(yè)數(shù): 13/80頁(yè)
文件大?。?/td> 340K
代理商: SAA5551PS/NNNN
1999 Oct 27
20
Philips Semiconductors
Preliminary specication
Standard TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
Pulse Width Modulator 5 Control Register (PWM5)
PW5E
activate this PWM (logic 1)
PW5V5 to PW5V0
pulse width modulator high time
Pulse Width Modulator 6 Control Register (PWM6)
PW6E
activate this PWM (logic 1)
PW6V5 to PW6V0
pulse width modulator high time
Pulse Width Modulator 7 Control Register (PWM7)
PW7E
activate this PWM (logic 1)
PW7V5 to PW7V0
pulse width modulator high time
ROM Bank (ROMBK)
STANDBY
standby activation bit
I2C-bus Slave Address Register (S1ADR)
ADR6 to ADR0
I2C-bus slave address to which the device will respond
GC
enable I2C-bus general call address (logic 1)
I2C-bus Control Register (S1CON)
CR2 to CR0
clock rate bits; CR<2:0>:
000 = 100 kHz bit rate
001 = 3.75 kHz bit rate
010 = 150 kHz bit rate
011 = 200 kHz bit rate
100 = 25 kHz bit rate
101 = 1.875 kHz bit rate
110 = 37.5 kHz bit rate
111 = 50 kHz bit rate
ENSI
enable I2C-bus interface (logic 1)
STA
START ag. When this bit is set in slave mode, the hardware checks the I2C-bus
and generates a START condition if the bus is free or after the bus becomes free.
If the device operates in master mode it will generate a repeated START
condition.
STO
STOP ag. If this bit is set in a master mode a STOP condition is generated. A
STOP condition detected on the I2C-bus clears this bit. This bit may also be set
in slave mode in order to recover from an error condition. In this case no STOP
condition is generated to the I2C-bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP ag is
cleared by the hardware.
BIT
FUNCTION
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