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參數(shù)資料
| 型號： | SAA3500H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital audio broadcast channel decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, MO-112, SOT-317-1, QFP-100 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 156K |
| 代理商： | SAA3500H |
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2000 Jun 14
13
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In phase 1, the level of the CMODE signal determines the microcontroller interface mode, while reset is asserted.
CMODE = HIGH defines I
2
C-bus mode, CMODE = LOW defines L3-bus mode. No transfers can be performed, as CCLK
must be HIGH.
In phase 2, which is for L3-bus mode of operation only, it is mandatory to take CMODE HIGH, then LOW again after reset
has been de-asserted, to correctly initialize the interface unit. This must occur before any L3-bus transfer (even to or from
other devices) is performed. CCLK shall remain HIGH during this phase.
In phase 3, the first transfer can be performed on the microcontroller interface.
Any deviation from these steps may result in undefined behaviour of the microcontroller interface, even with the
possibility of disturbing transfers to other devices connected to the control bus.
At a hardware reset, all writeable data items are forced to their default values.
The microcontroller interface provides access to all blocks, which generate or need control information. Selections on
the SAA3500H are at the sub-channel level, the required sub-channel parameters should be obtained via the Multiplex
Configuration Information (MCI), which is part of the FIC.
The CFIC window from the SAA3500H indicates FIC decoding. FIC data from the I
2
C/L3 interface will be invalid, if
CFIC = HIGH. It is therefore recommended to connect CFIC to a microcontroller interrupt input pin. With regard to the
real-time processing requirements, it is highly recommended to use a 16-bit microcontroller.
9.7.1
I
2
C-
BUS MODE
The implemented I
2
C-bus interface is of the 400 kbit/s, 7-bit address type. The CDATA output driver is of the ‘open drain’
type in order to be compliant with the I
2
C-bus specification. The device address is as follows:
Table 4
I
2
C-bus device address
Bit 7 to bit 1 comprise the 7-bit I
2
C-bus slave address, while bit 0 indicates the transfer direction of data and acknowledge
bits as follows:
Table 5
Read and write operation to the microcontroller in I
2
C-bus mode
Fundamentals of the I
2
C-bus interface protocol are shown in Fig.13.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
0
1
0
1
1
R/W
R/W
FUNCTION
REMARK
0
1
data from microcontroller to SAA3500H
data from SAA3500H to microcontroller
all acknowledge generated by SAA3500H
acknowledge for data generated by microcontroller
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