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參數資料
| 型號： | SAA2022 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | 磁帶格式和糾錯的數控系統(tǒng) |
| 文件頁數： | 35/52頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SAA2022 |
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February 1994
35
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Loadable registers
Table 14
AFLev.
AUX Flag threshold level. FLAGI goes HIGH for the AUX bytes whose flags are
≥
AFLev. AUXFLC will go HIGH if the
flags from either code word in the current segment are
≥
AFLev. The default value is 10.
Table 15
SPDDTY.
SPEED duty cycle register. If
μ
CSPD is active, this register determines the duty cycle of the speed signal.
The duty cycle is given by:
0 for 0% duty cycle
128 for 50% duty cycle
255 for 99.6% duty cycle.
The default value is 128.
Table 16
BYTCNT.
Byte counter for SYSINFO, AUX and Scratch Pad RAM
transfers. For SYSINFO:
values 0 to 31 access SYSINFO from the current segment.
values 32 to 63 access SYSINFO from the current +1 segment.
values 64 to 95 access SYSINFO from the current +2 segments.
values 96 to 127 access SYSINFO from the current +3 segments.
In Random access mode the SYSTEM ADDRESS is mapped on to BYTCNT as follows:
Table 17
SYSTEM ADDRES in Random access mode.
Table 18
RAACNT.
3
2
1
0
BIT
1
0
1
0
default value
7
6
5
4
3
2
1
0
BIT
1
0
0
0
0
0
0
0
default value
7
6
5
4
3
2
1
0
BIT
0
0
0
0
0
0
0
0
default value
7
6
5
4
3
2
1
0
BYTCNT
7
6
5
4
3
2
1
0
ROW
6
5
4
3
2
1
0
BIT
0
0
0
0
0
0
0
default value
Duty cycle
SPDDTY
100
×
256
=
%
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