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參數(shù)資料
| 型號： | SA9904BSA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Three Phase Power / Energy IC with SPI Interface |
| 中文描述： | 三相功率/能量芯片，SPI接口 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 106K |
| 代理商： | SA9904BSA |
and the SCK pin of the SA9904B. The DI and DO pins are the
serialdatainputandoutputpinsfortheSA9904B,respectively.
Table 1 lists the various register addresses. The SA9904B
contains nine 24 bit- registers representing the active energy,
reactive energy and the mains voltage for each phase. A tenth
24 bit register represents the mains frequency for any valid
phase. To remain compatible with the SA9604A three
addresses have been included. Any of the three addresses can
beusedtoaccessthefrequencyregister.
Register Access
ID
1
2
3
4
5
6
7
8
9
10
11
12
Register
Active Phase 1
Reactive Phase 1
Voltage Phase 1
Frequency
Active Phase 2
Reactive Phase 2
Voltage Phase 2
Frequency
Active Phase 3
Reactive Phase 3
Voltage Phase 3
Frequency
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
A5
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
A3
0
0
0
0
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
Header
bits
The 9 bits needed for register addressing can be padded with
leading zeros when the micro-controller requires a 8 bit SPI
wordlength.Thefollowingsequenceisvalid:
Figure 8 shows the SPI waveforms and figure 9 the timing
information. After the least significant digit of the address has
been entered on the rising edge of SCK, the output DO goes
lowwiththefallingedgeofSCK.Eachsubsequentfallingedge
transition on the SCK pin will validate the next data bit on the
DOpin.
The content of each register consists of 24 bits of data. The
MSBisshiftedoutfirst.
Data format
10
11
12
13
14
15
0 0 0 0 0 0 0 1 1 0 A5A4A3A2A1A0
9 8 7 6 5 4 3 2 1 0
1
1
A5
A0
A1
A2
A3
A4
0
D23
D22
D21
D1
D0
D23
D22
D1
D0
DO
DI
SCK
CS
Read command
Register address
Register Data
Next data register
High impedance
0
Dr-01647
Theheaderbits110(0x06)mustprecedethe6-bitaddressofthe
register being accessed. When CS is HIGH, data on pin DI is
clocked into the SA9904B on the rising edge of SCK. Figure 8
shows the data clocked into DI comprising of 1 1 0 A5 A4 A3 A2
A1 A0. Address locations A5 and A4 are included for
compatibilitywithfuturedevelopments.
Registers may be read individually and in any order. After a
register has been read, the contents of the next register value
willbeshiftedoutontheDOpinwitheverySCKclockcycle.Data
outputonDOwillcontinueuntilCSisinactive.
t1
t5
t3
SCK
DI
DO
CS
DR-01545
t4
t2
Parameter
t1
t3
t4
t2
t5
Max
1.160μs
Min
625ns
625ns
625ns
20ns
625ns
Description
SCK rising edge to DO valid
SCK min high time
SCK min low time
Setup time for DI and CS
before the rising edge of SCK
DI hold time
Figure 9: SPI Timing diagrams with timing information
Table 1: Register address
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