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參數(shù)資料
| 型號： | SA2400ABE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Single chip transceiver for 2.45 GHz ISM band |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 15/34頁 |
| 文件大?。?/td> | 325K |
| 代理商： | SA2400ABE |
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Philips Semiconductors
Product data
SA2400A
Single chip transceiver for 2.45 GHz ISM band
2002 Nov 04
15
I
2
I
1
I
2
I
1
V
1
V
2
CURRENT
V
PH
SR00602
I
ZOUT
VOLTAGE
Figure 4.
12. FUNCTIONAL DESCRIPTION
12.1 Main Fractional-N divider
The divider consists of a fully programmable bipolar prescaler
followed by a CMOS counter. Total divide ratios range from 512 to
65535.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented by the value of NF.
The accumulator works with modulo Q set by FM (Synthesizer
Register A). When the accumulator overflows, the overall division
ratio N will be increased by 1 to N + 1, the average division ratio
over Q main divider cycles (either 5 or 8) will be
Nfrac
N
NF
Q
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
12.2 Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a 3-bit binary counter. The
3-bit SM register (see Figure 5) determines which of the five output
pulses are selected as the main phase detector input.
SR02354
DIVIDE BY R
/2
/2
/2
/2
REFERENCE
INPUT
SM=“000”
SM=“001”
SM=“010”
SM=“011”
SM=“100”
TO
MAIN
PHASE
DETECTOR
Figure 5.
Reference Divider
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