參數(shù)資料
型號: SA2400ABE
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: Single chip transceiver for 2.45 GHz ISM band
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313-2, LQFP-48
文件頁數(shù): 10/34頁
文件大?。?/td> 325K
代理商: SA2400ABE
Philips Semiconductors
Product data
SA2400A
Single chip transceiver for 2.45 GHz ISM band
2002 Nov 04
10
9. SA2400A RECEIVER
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is
11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the
Receiver channel center frequency, as the IF output is at 0 Hz.
Table 6. SA2400A Receiver properties
T
amb
= 25
°
C; V
CC
= 3.3 V; f
LO
= 2.45 GHz.
Specification
Conditions
Min
Typ
Max
Units
RF input frequency range
Typical
2.4
2.5
GHz
S11 (RF input)
Incl balun+matching. 50
unbalanced. Note 3.
LNA in high gain (see reg. description 0x06)
LNA in low gain
–10
–7
dB
dB
Maximum Rx voltage gain
RF input to I or Q outputs
90
93
dB
Max RF input level
Including application, AGCTARGET = +5. Note 1.
–10
dBm
To maintain nominal IQ output levels as defined
below (“nominal I and Q output voltage”)
–20
dBm
IQ Output DC error (relative to signal,
5
μ
s after AGC set)
–80 dBm < P
input
< –20 dBm, 1 MHz sinewave
output. Note 3.
–20
dBc
AGC settling time
(indicated by AGC_SET digital
output)
Initiated by AGC_RESET input. Constant RF input
within this settling time. Begins after TX to RX
switching time. Measured from AGC_RESET
0–1
transition. AGC delay registers (0x05) at default or
smaller values. Note 2.
a) First instance
b) 2
nd
or subsequent instances
8
11
μ
s
μ
s
AGC Max Gain settling time
AGC forced to
GMAX by:
a) TX to RX mode transition.
(measured after 5
μ
s TX–RX settling time).
b)
Pulse on AGC_RESET pin
(measured from end of programming)
Note 2.
0
μ
s
3
μ
s
AGC Max Gain adjustment range
Note 2.
54 to 85, in steps of 1
dB
AGC error (I, Q signal levels)
RF input between –75 to –20 dBm. AGC_RESET
used. AGC delay registers (0x05) at default values.
a) Random (varies each AGC cycle)
b) Slow (varies with V
CC
, Temperature).
c) Static (fixed, part to part)
–3
–1
–1
3
1
1
dB
dB
dB
DC cancellation time
( ft
(after AGCRESET)
With constant RF input during this time. Note 3.
a) DC offset < 50% of output signal level
b) DC offset <10% of output signal level
8
13
μ
s
μ
s
TX to RX switching time
Output signal within 1 dB of final value,
frequency error within 25 ppm of final value. Note 3.
3
3.5
μ
s
Noise Figure
l b l
(Incl balun+matching)
t hi
Less than the piece-wise linear interpolation. Note 3.
P
input
=
–85 dBm (LNA in high gain mode)
–75 dBm
–60 dBm (LNA in low gain mode)
–45 dBm
7.5
7.5
24
24
9
9
25
25
dB
dB
dB
dB
Input IP3
(50
source resistance)
2 interfering tones of power P
interferer
each, at 13
and 23 MHz offsets from LO.
IP3 to be more than the piece-wise linear
interpolation:
P
interferer
= –39 dBm
Including matching, receiver at minimum gain.
–5
1
dBm
1 dB compression of wanted signal
–10
0
dBm
Desens by jammer
–45 dBm wanted signal at 1 MHz offset, +40 dBc
jammer at 25 MHz offset. Note 3.
1
dB
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