參數(shù)資料
型號(hào)： SA1630
廠商： NXP Semiconductors N.V.
英文描述： IF Quadrature Transceiver(IF正交收發(fā)器)
中文描述： 中頻正交收發(fā)器（中頻正交收發(fā)器）
文件頁(yè)數(shù)： 17/36頁(yè)
文件大小： 477K
代理商： SA1630
Philips Semiconductors
Application note
AN2003
SA1630 IF transceiver demonstration board
1999 Jan 05
17
ANSWERS TO COMMON QUESTIONS
Serial register and external AGC programming
Q: What is the easiest way to verify if the register programming
via the three wire bus is operating correctly
A: The easiest way to verify the functionality of the register
programming is to change the reference divide ratio from 22 MHz
to 8, 11, or 44 MHz while maintaining the Reference CLK input at
22 MHz. If the registers are being properly programmed, the LED
should dim, indicating an out of lock condition. If this does not
occur, check the three wire bus signals by selecting the “Repeat
Last Word” button from the software. Connect STROBE, CLOCK
and DATA to an oscilloscope. Trigger the scope from the
STROBE signal.
Q: What are the LLL, I offset, and Q offset registers for
A: In the predecessor to the SA1630, these registers were utilized
to adjust for DC offset errors in the Rx outputs and to provide a
feedback loop for correcting phase errors in the quadrature LO
signals. These registers are not used in the SA1630 and cannot
be programmed.
Q: Why is the Rx VGA Control programming table shown in the
datasheet to achieve the 70 dB of AGC dynamic range
discontinuous between decimal register values 15 and 23,
and 31 and 52
A: The AGC is composed of a combination of multiple amplifier
stages and attenuators. The sequence in the datasheet was
chosen to keep most of the gain in the early stages to optimize
the overall noise figure of the Rx path. Note this discontinuous
programming sequence when developing your own AGC control
software or hardware.
Phase Locked Loop
Q: Why doesn’t the LED on my board indicated a locked
condition
A: Check the following:
– Make sure that the PLL_ON mode select switch #2 on the
10 switch DIP sets this pin HIGH. (This is the OFF position on
the 10 switch DIP.)
– Make sure the jumper which connects the VCO to the loop
filter is in position.
– Check the CLK signal to ensure it is the same as that selected
in the software. If external programming is used, this will be
the default value of 22 MHz.
– Check to make sure the main divide ratio is set correctly at
LOin/2 (default = 352 MHz).
– Check to make sure that the supply voltage is reaching the
VCO.
– Monitor the VCO output at the LO port with a spectrum
analyzer to check if the signal is locked.
Q: What is the frequency range allowed for the reference
frequency crystal
A: The constraints on the IF frequency, together with the main and
reference divide ratio ranges, suggest the following:
– FXTALmin = (IFmin/main div max)*ref div min
= (70 MHz/511)*8
= 1.0959 MHz
– FXTALmax= (IFmax/main div min)*ref div max
= (400 MHz/64)*44
= 275 MHz
– Measurements of the reference divider output have shown that
the reference divider will work only up to approximately
200 MHz.
Q: Why is the VCO center frequency at 704 MHz when the IF
frequency is 352 MHz
A: Prior to the programmable main divider, there is an additional /2
divider internal to the IC.
Q: Why is the VCO mounted on the backside of the PCB
A: At high AGC settings, the Rx path has approximately 85 dB of
voltage gain. Harmonics of the VCO could potentially make their
way to the RF input of the Receiver and saturate the AGC amps.
The VCO was placed on the back side of the PCB in order to
minimize the probability of this occurring.
Q: What is the 50
T-network for at the LO port of the PCB
A: The LO port on the PCB is for monitoring the PLL performance
with a spectrum analyzer. The spectrum analyzer will present a
50
impedance to this port. The objective of the T-network is to
present a load of approximately 50
to the 50
output of the
VCO and split the power delivered from the VCO evenly between
the spectrum analyzer and the LO input circuitry. An 18
resistor is placed in series with both the 50
LO input and the
50
spectrum analyzer, thus creating two parallel 68
loads or
a 34
combined load. An additional 18
resistor is also placed
in series with this, which then presents 34 + 18 = 52
to the
VCO output.
Q: What is the sensitivity of the VCO
A: The Murata MQE704 MHz VCO has a sensitivity of
approximately 10.25 MHz/V.
Q: My PLL is not locking. How can I ensure that the proper
signals are reaching the phase detector
A: The SA1630 can be programmed into several test modes via the
three wire bus interface. These test modes will redirect the
divided down input signals of the phase detector to the lock
detect pin where they can be verified. (See the datasheet for
details.)
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