參數(shù)資料
型號: S75PL127JCFBFWB2
廠商: Spansion Inc.
英文描述: Power supply woltage of 2.7 to 3.1 volt
中文描述: 功率2月7號至三月一日伏的電源woltage
文件頁數(shù): 77/183頁
文件大小: 1409K
代理商: S75PL127JCFBFWB2
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁
78
S29GLxxxN MirrorBit
TM
Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
A d v a n c e I n f o r m a t i o n
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm
MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be
programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are avail-
able. Note that each access time has a specific operating voltage range (V
CC
) and
an I/O voltage range (V
IO
), as specified in the
“Product Selector Guide”
section.
The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a
single 3.0 volt power supply
for both read and
write functions. In addition to a V
CC
input, a high-voltage
accelerated program
(
WP#/
ACC)
input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the
JEDEC single-
power-supply Flash standard
. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or monitor the
Ready/Busy#
(RY/BY#)
output to determine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The
Enhanced
VersatileI/O
(V
IO
) control allows the host system to set the
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the V
IO
pin. This allows the device to operate in a 1.8 V or 3 V system environ-
ment as required.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions.
Persistent Sector
Protection
provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at V
CC
.
Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The
Erase Suspend/Erase Resume
feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The
Program Suspend/Program Resume
fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
相關(guān)PDF資料
PDF描述
S7AH-06E NON-ISOLATED DC/DC CONVERTERS 4.5 13.2V Input / 1.0 ? 3.3V Output / 6A
S7AH-08B250 NON-ISOLATED DC/DC CONVERTERS 5V Input / 0.9V - 3.3V Output / 8A
S7AH-08B330 NON-ISOLATED DC/DC CONVERTERS 5V Input / 0.9V - 3.3V Output / 8A
S7AH-08B NON-ISOLATED DC/DC CONVERTERS 5V Input / 0.9V - 3.3V Output / 8A
S7AH-08B120 NON-ISOLATED DC/DC CONVERTERS 5V Input / 0.9V - 3.3V Output / 8A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S75PL127JCFBFWB3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCFBFWU0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCFBFWU2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCFBFWU3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127NBF 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP)