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參數(shù)資料
| 型號(hào)： | S71PL032J80-07 |
| 廠商： | Spansion Inc. |
| 英文描述： | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| 中文描述： | 堆疊式多芯片產(chǎn)品，閃存和RAM |
| 文件頁(yè)數(shù)： | 78/196頁(yè) |
| 文件大?。?/td> | 5729K |
| 代理商： | S71PL032J80-07 |
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78
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
A d v a n c e I n f o r m a t i o n
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector is actively erasing (that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have
been selected for erasure. (The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table
19
to compare outputs for DQ2 and DQ6.
Figure 7
shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle
Bit II explains the algorithm. See also the DQ6: Toggle Bit I.
Figure 19
shows the
toggle bit timing diagram.
Figure 20
shows the differences between DQ2 and DQ6
in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to
Figure 7
for the following discussion. Whenever the system initially be-
gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
Note:
The system should recheck the toggle bit even if DQ5 = “1” because the toggle
bit may stop toggling as DQ5 changes to “1.” See the DQ6: Toggle Bit I and DQ2:
Toggle Bit II for more information.
Figure 7. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1
No
Yes
Toggle Bit
= Toggle
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle
Read Byte Twice
(DQ7–DQ0)
Address = VA
Read Byte
(DQ7–DQ0)
Address =VA
Read Byte
(DQ7–DQ0)
Address =VA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL032J80-0P | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032JA0 | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032JA0-0F | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032JA0-0K | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032JA0-0Z | STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL032J80-0F | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80-0P | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM |
| S71PL032J80BAW0Z0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW0Z2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
| S71PL032J80BAW0Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Based MCPs |
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