參數(shù)資料
型號： S71PL032J04-0K
廠商： Spansion Inc.
英文描述： STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
中文描述： 堆疊式多芯片產(chǎn)品，閃存和RAM
文件頁數(shù)： 6/196頁
文件大?。?/td> 5729K
代理商： S71PL032J04-0K
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6
S71PL254/127/064/032J_00_A6 November 22, 2004
A d v a n c e I n f o r m a t i o n
Operating Range .................................................................................................117
Table 35. DC Electrical Characteristics
(Over the Operating Range) ..............................................117
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . 118
AC Test Loads and Waveforms . . . . . . . . . . . . . 118
Figure 43. AC Test Loads and Waveforms............................ 118
Table 36. Switching Characteristics .....................................119
Switching Waveforms . . . . . . . . . . . . . . . . . . . . 120
Figure 44. Read Cycle 1 (Address Transition Controlled)........ 120
Figure 45. Read Cycle 2 (OE# Controlled) ........................... 120
Figure 46. Write Cycle 1 (WE# Controlled) .......................... 121
Figure 47. Write Cycle 2 (CE#1 or CE2 Controlled) ............... 122
Figure 48. Write Cycle 3 (WE# Controlled, OE# Low)............ 123
Figure 49. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low).. 123
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 37. Truth Table ........................................................124
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Functional Description . . . . . . . . . . . . . . . . . . . . . 126
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 126
AC Characteristics and Operating Conditions . 127
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . 128
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 129
Read Timings ......................................................................................................129
Figure 50. Read Cycle....................................................... 129
Figure 51. Page Read Cycle (8 Words Access)...................... 130
Write Timings .....................................................................................................131
Figure 52. Write Cycle #1 (WE# Controlled) (See Note 8) ..... 131
Figure 53. Write Cycle #2 (CE# Controlled) (See Note 8)...... 132
Deep Power-down Timing .............................................................................132
Figure 54. Deep Power Down Timing................................... 132
Power-on Timing ...............................................................................................132
Figure 55. Power-on Timing............................................... 132
Provisions of Address Skew ............................................................................133
Figure 56. Read ............................................................... 133
Figure 57. Write............................................................... 133
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Functional Description . . . . . . . . . . . . . . . . . . . . . 135
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 135
Power Down .......................................................................................................135
Power Down Program Sequence .................................................................136
Address Key .......................................................................................................136
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 137
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 137
Power Down Parameters ................................................................................141
Other Timing Parameters ...............................................................................141
AC Test Conditions .........................................................................................142
AC Measurement Output Load Circuits ...................................................142
Figure 58. AC Output Load Circuit – 16 Mb .......................... 142
Figure 59. AC Output Load Circuit – 32 Mb and 64 Mb........... 142
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 143
Read Timings ......................................................................................................143
Figure 60. Read Timing #1 (Basic Timing)........................... 143
Figure 61. Read Timing #2 (OE# Address Access................. 143
Figure 62. Read Timing #3 (LB#/UB# Byte Access) ............. 144
Figure 63. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 144
Figure 64. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 145
Write Timings .....................................................................................................145
Figure 65. Write Timing #1 (Basic Timing).......................... 145
Figure 66. Write Timing #2 (WE# Control).......................... 146
Figure 67. Write Timing #3-1(WE#/LB#/UB# Byte
Write Control)................................................................. 146
Figure 68. Write Timing #3-3 (WE#/LB#/UB# Byte
Write Control)................................................................. 147
Figure 69. Write Timing #3-4 (WE#/LB#/UB# Byte
Write Control)................................................................. 147
Read/Write Timings ..........................................................................................148
Figure 70. Read/Write Timing #1-1 (CE1# Control) ............. 148
Figure 71. Read / Write Timing #1-2
(CE1#/WE#/OE# Control)................................................ 148
Figure 72. Read / Write Timing #2 (OE#, WE# Control) ....... 149
Figure 73. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control) ........................................ 149
Figure 74. Power-up Timing #1......................................... 150
Figure 75. Power-up Timing #2......................................... 150
Figure 76. Power Down Entry and Exit Timing ..................... 150
Figure 77. Standby Entry Timing after Read or Write............ 151
Figure 78. Power Down Program Timing (for 32M/64M Only). 151
SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 152
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Functional Description . . . . . . . . . . . . . . . . . . . . . 153
4M Version F, 4M version G, 8M version C .........................................153
Byte Mode ............................................................................................................153
Functional Description . . . . . . . . . . . . . . . . . . . . . 154
8M Version D .................................................................................................154
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 155
Recommended DC Operating Conditions (Note 1) ..............................155
Capacitance (f=1MHz, T
A
=25
°
C) ..................................................................155
DC Operating Characteristics ......................................................................155
Common ..........................................................................................................155
DC Operating Characteristics ......................................................................156
4M Version F ..................................................................................................156
DC Operating Characteristics ......................................................................156
4M Version G .................................................................................................156
DC Operating Characteristics ......................................................................157
8M Version C .................................................................................................157
DC Operating Characteristics ......................................................................157
8M Version D .................................................................................................157
AC Operating Conditions . . . . . . . . . . . . . . . . . . 158
Test Conditions .................................................................................................158
Figure 79. AC Output Load................................................ 158
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158
Read/Write Characteristics (V
CC
=2.7-3.3V) .............................................158
Data Retention Characteristics (4M Version F) ......................................159
Data Retention Characteristics (4M Version G) .....................................160
Data Retention Characteristics (8M Version C) .....................................160
Data Retention Characteristics (8M Version D) .....................................160
Timing Diagrams ................................................................................................160
Figure 80. Timing Waveform of Read Cycle(1) (Address Controlled,
CS#1=OE#=V
IL
, CS2=WE#=V
IH
, UB# and/or LB#=V
IL
)...... 160
Figure 81. Timing Waveform of Read Cycle(2) (WE#=V
IH
, if BYTE#
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