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參數(shù)資料
| 型號： | S29PL127N65GFWW03 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 8M X 16 FLASH 3V PROM, 65 ns, PBGA64 |
| 封裝： | 8 X 11.60 MM, LEAD FREE, FBGA-84 |
| 文件頁數(shù)： | 21/74頁 |
| 文件大?。?/td> | 1968K |
| 代理商： | S29PL127N65GFWW03 |
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June 6, 2007 S29PL-N_00_A5
S29PL-N MirrorBit
Flash Family
21
D a t a
S h e e t
( P r e l i m i n a r y )
7.1.1
Dual Chip Enable Device Description and Operation (PL129N Only)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate processors with a
limited addressable range. This product operates as two separate devices in a single package and requires
the processor to address half of the memory space with one chip enable and the remaining memory space
with a second chip enable. For more details on the addressing features of the Dual CE# device refer to
Table 6.3 on page 19
for the PL129N Sector and Memory Address Map.
Dual chip enable products must be setup appropriately for each operation. To place the device into the active
state either CE1# or CE2# must be set to V
IL
. To place the device in standby mode, both CE1# and CE2#
must be set to V
IH
.
Table 7.2
describes the required state of each control pin for any particular operation.
Legend
L = Logic Low = V
IL
VID = 11.5–12.5 V
X = Don’t Care
A
IN
= Address In
D
OUT
= Data Out
H = Logic High = V
IH
V
HH
= 8.5 – 9.5 V
SA = Sector Address
D
IN
= Data In
Notes
1. The sector and sector unprotect functions may also be implemented by programming equipment.
2. WP#/ACC must be high when writing to the upper two and lower two sectors.
7.2
Asynchronous Read
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for
read access until the command register contents are altered.
7.2.1
Non-Page Random Read
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The
output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming
the addresses have been stable for at least t
ACC
– t
OE
time).
Table 7.2
Dual Chip Enable Device Operation
Operation
CE1#
CE2#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A21 – A0)
DQ15 – DQ0
Read
L
H
L
H
H
X
A
IN
D
OUT
H
L
Write
L
H
H
L
H
X
(Note 2)
A
IN
D
IN
H
L
Standby
H
H
X
X
H
X
X
High-Z
Output Disable
L
L
H
H
H
X
X
High-Z
Reset
X
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect
(High Voltage)
X
X
X
X
V
ID
X
A
IN
D
IN
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