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參數(shù)資料
| 型號(hào)： | S29GL128P90FAI010 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 90 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FBGA-64 |
| 文件頁(yè)數(shù)： | 19/77頁(yè) |
| 文件大小： | 2121K |
| 代理商： | S29GL128P90FAI010 |
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November 8, 2007 S29GL-P_00_A7
S29GL-P MirrorBit
Flash Family
19
D a t a
S h e e t
( P r e l i m i n a r y )
Note
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges
that are not explicitly listed (such as SA001-SA510) have sector starting and ending addresses that form the same pattern as all other
sectors of that size. For example, all 128 Kb sectors have the pattern xxx0000h-xxxFFFFh.
7.
Device Operations
This section describes the read, program, erase, handshaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns
into the command registers (see
Table 12.1
through
Table 12.4
). The command register itself does not
occupy any addressable memory location; rather, it is composed of latches that store the commands, along
with the address and data information needed to execute the command. The contents of the register serve as
input to the internal state machine and the state machine outputs dictate the function of the device. Writing
incorrect address and data values or writing them in an improper sequence may place the device in an
unknown state, in which case the system must pull the RESET# pin low or power cycle the device to return
the device to the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation.
Table 7.1
describes the required state of each
control pin for any particular operation.
Legend
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
HH
= 11.5–12.5V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes
1. Addresses are AMax:A0 in word mode; A
Max
:A-1 in byte mode.
2. If WP# = V
IL
, on the outermost sector remains protected. If WP# = V
IH
, the outermost sector is unprotected. WP# has an internal pull-up; when unconnected,
WP# is at V
IH
. All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered.)
3. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm.
Table 6.4
S29GL128P Sector & Memory Address Map
Uniform Sector
Size
Sector
Count
Sector
Range
Address Range (16-bit)
Notes
64 Kword/128 Kb
128
SA00
0000000h - 000FFFFh
Sector Starting Address
:
:
SA127
07F0000 - 7FFFFF
Sector Ending Address
Table 7.1
Device Operations
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 1)
DQ0–DQ7
DQ8–DQ15
BYTE#= V
IH
D
OUT
(Note 3)
BYTE#= V
IL
Read
L
L
H
H
X
A
IN
A
IN
A
IN
X
D
OUT
(Note 3)
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
L
H
L
H
(Note 2)
Accelerated Program
L
H
L
H
V
HH
H
(Note 3)
(Note 3)
Standby
V
CC
±
0.3 V
L
X
X
V
CC
±
0.3 V
H
High-Z
High-Z
Output Disable
H
H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
High-Z
High-Z
High-Z
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