參數(shù)資料
型號(hào): S29AL016M90FAI020
廠商: SPANSION LLC
元件分類: DRAM
英文描述: Hex Schmitt Trigger; Package: SOEIAJ-14; No of Pins: 14; Container: Rail; Qty per Container: 50
中文描述: 1M X 16 FLASH 3V PROM, 90 ns, PBGA64
封裝: 13 X 11 MM, FBGA-64
文件頁數(shù): 3/59頁
文件大?。?/td> 1917K
代理商: S29AL016M90FAI020
April 21, 2004 S29AL016M_00A4
S29AL016M
4
Table of Contents
S29AL016M 2
General Description 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 11
Table 1. S29AL016M Device Bus Operations .........................11
Word/Byte Configuration ....................................................................11
Requirements for Reading Array Data ............................................11
Writing Commands/Command Sequences ...................................12
Program and Erase Operation Status ..............................................12
Standby Mode .........................................................................................12
Automatic Sleep Mode .........................................................................13
RESET#: Hardware Reset Pin ............................................................13
Output Disable Mode ...........................................................................13
Table 2. Sector Address Tables (Model 01, Top Boot Device) ...14
Table 3. Sector Address Tables (Model 02, Bottom Boot Device) .
15
Autoselect Mode ...................................................................................15
Table 4. Autoselect Codes (High Voltage Method) ..................16
Sector Protection/Unprotection .......................................................16
Temporary Sector Unprotect ...........................................................17
Figure 1. Temporary Sector Unprotect Operation................... 17
Figure 2. In-System Single High Voltage Sector Protect/
Unprotect Algorithms ........................................................ 18
SecSi (Secured Silicon) Sector Flash Memory Region ................19
Table 5. SecSi Sector Addressing ........................................19
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ...........................................................................19
Figure 3. SecSi Sector Protect Verify ................................... 20
Common Flash Memory Interface (CFI) .......................................20
Table 6. CFI Query Identification String ...............................21
Table 7. System Interface String .........................................22
Table 8. Device Geometry Definition ....................................22
Table 9. Primary Vendor-Specific Extended Query .................23
Hardware Data Protection ................................................................23
Low V
CC
Write Inhibit .......................................................................23
Write Pulse “Glitch” Protection ......................................................23
Logical Inhibit .........................................................................................24
Power-Up Write Inhibit .....................................................................24
Command Definitions . . . . . . . . . . . . . . . . . . . . . .24
Reading Array Data .............................................................................24
Reset Command ...................................................................................24
Autoselect Command Sequence ......................................................25
Word/Byte Program Command Sequence ...................................25
Unlock Bypass Command Sequence ...............................................26
Figure 4. Program Operation .............................................. 27
Chip Erase Command Sequence ......................................................27
Sector Erase Command Sequence ..................................................28
Erase Suspend/Erase Resume Commands ....................................28
Figure 5. Erase Operation .................................................. 30
Program Suspend/Program Resume Command Sequence ......30
Figure 6. Program Suspend/Program Resume....................... 31
Command Definitions Tables ...........................................................32
Command Definitions (x16 Mode, BYTE# = V
IH
).................... 32
Command Definitions (x8 Mode, BYTE# = V
IL
)...................... 33
Write Operation Status . . . . . . . . . . . . . . . . . . . . .34
DQ7: Data# Polling ..............................................................................34
Figure 7. Data# Polling Algorithm ....................................... 35
RY/BY#: Ready/Busy# ..........................................................................35
DQ6: Toggle Bit I ..................................................................................36
DQ2: Toggle Bit II ................................................................................36
Reading Toggle Bits DQ6/DQ2 .........................................................37
Figure 8. Toggle Bit Algorithm ............................................ 38
DQ5: Exceeded Timing Limits ..........................................................38
DQ3: Sector Erase Timer ..................................................................39
Table 12. Write Operation Status ....................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . .40
Figure 9. Maximum Negative Overshoot Waveform................ 40
Figure 10. Maximum Positive Overshoot Waveform................ 40
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 11. Test Setup........................................................ 42
Table 13. Test Specifications ............................................. 42
Figure 12. Input Waveforms and Measurement Levels............ 42
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .43
Read Operations ...................................................................................43
Figure 13. Read Operations Timings .................................... 43
Hardware Reset (RESET#) ................................................................44
Figure 14. RESET# Timings................................................ 44
Erase/Program Operations ................................................................45
Figure 15. Program Operation Timings................................. 46
Figure 16. Chip/Sector Erase Operation Timings.................... 47
Figure 17. Data# Polling Timings
(During Embedded Algorithms)........................................... 48
Figure 18. Toggle Bit Timings
(During Embedded Algorithms)........................................... 48
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ................................................. 49
Figure 20. Temporary Sector Unprotect/Timing Diagram ........ 49
Figure 21. Sector Protect/Unprotect Timing Diagram.............. 50
Figure 22. Alternate CE# Controlled Write Operation Timings.. 52
Erase and Programming Performance . . . . . . . . .53
TSOP Pin and BGA Package Capacitance . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .54
TS 048—48-Pin Standard TSOP ......................................................54
TSR048—48-Pin Reverse TSOP ......................................................55
FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)
6 x 8 mm Package .................................................................................56
LAA064—64-Ball Fortified Ball Grid Array (BGA)
13 x 11 mm Package ...............................................................................57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58
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