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參數(shù)資料
| 型號： | S25FL004AOLMAI000 |
| 廠商： | Spansion Inc. |
| 英文描述： | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存 |
| 文件頁數(shù)： | 16/39頁 |
| 文件大小： | 945K |
| 代理商： | S25FL004AOLMAI000 |
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S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
Instructions
All instructions, addresses, and data are shifted in and out of the device, starting
with the most significant bit. Serial Data Input (SI) is sampled on the first rising
edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one-
byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (SI), each bit being latched on the rising edges of Serial
Clock (SCK). The instruction set is listed in
Table 4, on page 15
.
Every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the in-
struction sequence is shifted in.
In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Read
Data Bytes at higher speed (FAST_READ) and Read Identification (RDID) instruc-
tions, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (CS#) can be driven High after any bit of the data-out sequence is
being shifted out to terminate the transaction.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write
Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc-
tion, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select
(CS#) must driven High when the number of clock pulses after Chip Select (CS#)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle,
Program cycle or Erase cycle are ignored, and the internal Write Status Register
cycle, Program cycle or Erase cycle continues unaffected
相關PDF資料 |
PDF描述 |
|---|---|
| S25FL004AOLNFI001 | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLNFI002 | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLNFI003 | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLNAI002 | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLNAI003 | 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S25FL004AOLMAI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLMAI002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLMAI003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLMFI000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004AOLMFI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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