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S2076
QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
TRANSMITTER DESCRIPTION
The transmitter section of the S2076 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Transmitter
functionalities are shown schematically in Figure 3.
Four channels are provided with a variety of options
regarding input clocking and loopback. The transmit-
ters operate at 1.062 GHz, 10 or 20 times the refer-
ence clock frequency.
Data Input
The S2076 has been designed to simplify the paral-
lel interface data transfer and provides flexibility in
the clocking of parallel data. Prior implementations
of this function have either forced the user to syn-
chronize transmit data to the reference clock or to
provide the output clock as a reference to the PLL,
resulting in increased jitter at the serial interface.
The S2076 incorporates a unique FIFO structure
which enables the user to provide a “clean” refer-
ence source for the PLL and to accept a separate
external clock which is used exclusively to reliably
clock data into the device.
The S2076 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock. See Table 2.
Data to be input to the S2076 should be coded to
insure transition density and DC balance. Data is
input to each channel of the S2076 as a 10 bit wide
word. An input FIFO and a clock input,
TBCx, are
provided for each channel of the S2076. The device
can operate in two different modes. The S2076 can
be configured to use either the TBCx (TBC MODE)
input or the REFCLK input (REFCLK MODE). Table
1 provides a summary of the input modes for the
S2076.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the parallel 10-bit interface. The
TBC signal is used to clock the data into an internal
holding register and the S2076 synchronizes its in-
ternal data flow to insure stable operation. REFCLK,
not TBCx, is used as the reference for the DIN PLL.
This insures minimum jitter on the high speed serial
data stream.
The TBC must be frequency locked to
REFCLK, but
may have an arbitrary but fixed phase relationship.
Adjustment of internal timing of the S2076 is per-
formed during reset. Once synchronized, the S2076
can tolerate up to
±
3ns of phase drift between TBC
and REFCLK.
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Table 1. Input Modes
Table 2. Operating Rates
REFCLK
S2076
106.25 MHz or 53.125 MHz
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
Figure 5. DIN Clocking with TBC
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
Note: SDR = Serial Data Rate.
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