24
EPSON
S1C6P366 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.4 Operating voltage
The S1C6P366 generates the VD1 voltage internally for the oscillation circuit in order to stabilize oscilla-
tion. In the S1C6P366, the VD1 voltage is used only for the oscillation circuit and the voltage level is fixed
at 2.05
±0.3 V.
Therefore, setting of the VDC register (FF00HD0) required in the mask ROM model is invalidated and
does not affect the VD1 voltage level.
When using the S1C6P366 as a development tool for the S1C63358/63158, switch the operating voltage
using the VDC register according to the control sequence of the model (refer to the "Technical Manual").
Furthermore, internal logic circuits (including the OSC3 oscillation circuit) of the S1C6P366 except for the
OSC1 oscillation circuit operate with the source voltage supplied between the VDD and VSS terminal.
4.3.5 Switching operating clock
The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register).
When using OSC3 as the CPU system clock, first turn the OSC3 oscillation ON and then switch the clock
after waiting 5 msec or more for oscillation stabilization.
When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock.
OSC1
→ OSC3
OSC3
→ OSC1
1. Set OSCC to "1" (OSC3 oscillation ON).
1. Set CLKCHG to "0" (OSC3
→ OSC1).
2. Maintain 5 msec or more.
2. Set OSCC to "0" (OSC3 oscillation OFF).
3. Set CLKCHG to "1" (OSC1
→ OSC3).
4.3.6 Clock frequency and instruction execution time
Table 4.3.6.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.3.6.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC3: 4 MHz
Instruction execution time (
sec)
1-cycle instruction
2-cycle instruction
3-cycle instruction
61
122
183
0.5
1
1.5