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參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁數(shù)： | 63/208頁 |
| 文件大小： | 1561K |
| 代理商： | S1C6F567D0A0100 |
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S1C6F567 TECHNICAL MANUAL
EPSON
147
CHAPTER 7: SUMMARY OF NOTES
(2) The K13 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K13 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
Output port
(1) When using an output port (R00–R03, R10–R13) for special output, fix the corresponding data register
(R00–R03, R10–R13) at "1" and the high impedance control register (R00HIZ–R03HIZ, R10HIZ–
R13HIZ) at "0" (data output).
Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the data registers when the special output has been selected.
Be aware that the output terminal shifts into high impedance status when "1" is written to the high
impedance control register.
(2) A hazard may occur when the TOUT, FOUT , BZ or XBZ signal is turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output.
Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
I/O port
(1) When in the input mode, I/O ports are changed from low to high by pull-up resistor, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 k
(2) When special output (CL, FR) has been selected, a hazard may occur when the signal is turned ON or
OFF.
LCD driver
(1) When a program that access no memory mounted area (F078H–F0FFH, F178H–F1FFH, F201H, F203H,
, F277H) is made, the operation is not guaranteed.
(2) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,
there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF
because these are set so that the display goes OFF.
Clock timer
Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
Stopwatch timer
When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
sec (1/4 cycle of 256 Hz).
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
(2) The programmable timer actually enters RUN/STOP status in synchronization with the falling edge
of the input clock after writing to the PTRUN0/PTRUN1 register. Consequently, when "0" is written to
the PTRUN0/PTRUN1 register, the timer enters STOP status at the point where the counter is
decremented (-1). The PTRUN0/PTRUN1 register maintains "1" for reading until the timer actually
stops.
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