參數(shù)資料
型號(hào)： S1C63653F
元件分類： 微控制器/微處理器
英文描述： 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, CQFP100
封裝： CERAMIC, QFP15-100
文件頁數(shù)： 96/121頁
文件大?。?/td> 1127K
代理商： S1C63653F
68
EPSON
S1C63653 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
4.10.8 Control of TOUT output
The programmable timer can generate a TOUT signal from the timer underflow and compare match
signals. The TOUT signal is generated by dividing the underflow signal by 2 in the normal mode. In the
PWM mode, the PWM signal generated by timer 0/1 is output as the TOUT signal. It is possible to select
which timer output is to be used by the TOUT output channel selection register CHSEL0.
Table 4.10.8.1 Selecting a timer for TOUT output
CHSEL0
1
0
TOUT output timer
Timer 1
Timer 0
Select timer 1 when generating the TOUT signal from the 16-bit timer output.
The TOUT signal can be output from the R02 output port terminal.
Figure 4.10.8.1 shows the configuration of the output port R02.
Data
bus
Register
PTOUT
Register
R02
TOUT
R02
(TOUT)
Register
R02HIZ
Fig. 4.10.8.1 Configuration of R02
The output of a TOUT signal is controlled by the PTOUT register. When "1" is written to the PTOUT
register, the TOUT signal is output from the R02 output port terminal and when "0" is written, the
terminal goes to a high (VDD) level. However, the data register R02 must always be "1" and the high
impedance control register R02HIZ must always be "0" (data output state).
Since the TOUT signal is generated asynchronously from the PTOUT register, a hazard within 1/2 cycle is
generated when the signal is turned on and off by setting the register.
Figure 4.10.8.2 shows the output waveform of the TOUT signal.
R02HIZ register
R02 register
PTOUT register
TOUT output
Fix at "0"
Fix at "1"
"1"
"0"
Fig. 4.10.8.2 Output waveform of the TOUT signal
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