參數(shù)資料
型號： S1C63406D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC103
封裝： DIE-103
文件頁數(shù)： 68/151頁
文件大?。?/td> 1171K
代理商： S1C63406D0A0100
S1C63406/408 TECHNICAL MANUAL
EPSON
15
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.4 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.4.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.
Table 2.2.4.1 Initial values
Name
Data register A
Data register B
Extension register EXT
Index register X
Index register Y
Program counter
Stack pointer SP1
Stack pointer SP2
Zero flag
Carry flag
Interrupt flag
Extension flag
Queue register
CPU core
Symbol
A
B
EXT
X
Y
PC
SP1
SP2
Z
C
I
E
Q
Number of bits
4
8
16
8
1
16
Setting value
Undefined
0110H
Undefined
0
Undefined
Name
RAM
Display memory
Other pheripheral circuits
Peripheral circuits
Number of bits
4
–
Setting value
Undefined
See Section 4.1, "Memory Map".
2.2.5 Terminal settings at initial resetting
The output port (R) terminals and I/O port (P) terminals are shared with special output terminals and
input/output terminals of the serial interface. These functions are selected by the software. At initial
reset, these terminals are set to the general purpose output port terminals and I/O port terminals. Set
them according to the system in the initial routine. In addition, take care of the initial status of output
terminals when designing a system.
Table 2.2.5.1 shows the list of the shared terminal settings.
Table 2.2.5.1 List of shared terminal settings
Terminal
name
R10
R11
R12
R13
P20
P21
P22
P23
Terminal status
at initial reset
R10 (High level output)
R11 (High level output)
R12 (High level output)
R13 (High level output)
P20 (Input mode & Pulled-up)
P21 (Input mode & Pulled-up)
P22 (Input mode & Pulled-up)
P23 (Input mode & Pulled-up)
Special output
TOUT
FOUT
TOUT
FOUT
Serial I/F
Master
Slave
Async.
SIN(I)
SOUT(O) SOUT(O) SOUT(O)
SCLK(O) SCLK(I)
SRDY(O)
For setting procedure of the functions, see explanations for each of the peripheral circuits.
2.3 Test Terminal (TEST)
This is the terminal used for the factory inspection of the IC. During normal operation, connect the TEST
terminal to VDD.
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