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參數(shù)資料
| 型號： | S1C63406D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC103 |
| 封裝： | DIE-103 |
| 文件頁數(shù)： | 27/151頁 |
| 文件大小： | 1171K |
| 代理商： | S1C63406D0A0100 |
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114
EPSON
S1C63406/408 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(4) When a parity error or flaming error is generated during receiving in the asynchronous mode, the
receiving error interrupt factor flag ISER is set to "1" prior to the receive completion interrupt factor
flag ISRC for the time indicated in Table 5.2.1. Consequently, when an error is generated, you should
reset the receiving complete interrupt factor flag ISRC to "0" by providing a wait time in error process-
ing routines and similar routines.
When an overrun error is generated, the receiving complete interrupt factor flag ISRC is not set to "1"
and a receiving complete interrupt is not generated.
Table 5.2.1 Time difference between ISER and ISRC on error generation
Clock source
Time difference
fOSC3 / n
Programmable timer
1/2 cycles of fOSC3 / n
1 cycle of timer 1 underflow
(5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary
to turn the OSC3 oscillation ON, prior to using the serial interface.
A time interval of 5 msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation
stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an
adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiv-
ing of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and
on the externally attached parts. Refer to the oscillation start time example indicated in Chapter 7,
"Electrical Chracteristics".)
At initial reset, the OSC3 oscillation circuit is set to OFF status.
(6) Be aware that the maximum clock frequency for the serial interface is limited to 2 MHz.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be ON for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 100 sec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned OFF because SVD operation increase current consump-
tion.
Heavy load protection function
Be aware that current consumption increases in the heavy load protection mode.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine.
Further, when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is
set, all the interrupts including NMI are masked and interrupts cannot be accepted until the other one
is set.
(4) When using the SLEEP function, set the following flag and the registers for the K0x port to be used to
cancel SLEEP status before executing the SLP instruction.
Interrupt flag (I flag) = "1" (interrupts are enabled)
Interrupt selection register SIK0x = "1" (the K0x input port interrupt is selected)
Interrupt mask register EIK0x = "1" (the K0x input port interrupt is enabled)
Noise rejector selection register K0NR1–K0NR0 = "00" (noise rejector is bypassed)
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