I-106
EPSON
S1C62N33 TECHNICAL HARDWARE
CHAPTER 5: SUMMARY OF NOTES
(2) SVDON resides in the same bit at the same address as
SVDDT, and one or the other is selected by write or read
operation. This means that arithmetic operations (AND,
OR, ADD, SUB and so forth) cannot be used for SVDON
control.
(3) Select one of the following software processing to return
to the normal mode after a heavy load has been driven in
the heavy load protection mode.
After heavy load drive is completed, return to the
normal mode after at least one second has elapsed.
After heavy load drive is completed, switch SVD ON
and OFF (at least 100 s is necessary for the ON
status) and then return to the normal mode.
(4) When the SVD is to be turned on during operation in the
heavy load protection mode, limit the ON time to 10 ms
per second of operation time.
(1) If the bit data of SE2 changes while SCLK is in the mas-
ter mode, a hazard will be output to the SCLK pin. If this
poses a problem for the system, be sure to set the SCLK
to the external clock if the bit data of SE2 is to be
changed.
(2) Be sure that read-out of the interrupt factor flag (ISIO) is
done only when the serial port is in the STOP status
(SIOF = "0") and the DI status (interrupt flag = "0"). If
read-out is performed while the serial data is in the RUN
status (during input or output), the data input or output
will be suspended and the initial status resumed. Read-
out during the EI status (interrupt flag = "1") causes
malfunctioning.
(3) When using the serial interface in the master mode, the
synchronous clock uses the CPU system clock. Accord-
ingly, do not change the system clock (fosc1
fosc3)
while the serial interface is operating.
(4) Perform data writing/reading to data registers SD0–SD7
only while the serial interface is halted (i.e., the synchro-
nous clock is neither being input or output).
Serial interface