參數(shù)資料
型號(hào)： S1C60L16F0A0100
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP14-80
文件頁(yè)數(shù)： 93/105頁(yè)
文件大小： 841K
代理商： S1C60L16F0A0100
78
EPSON
S1C60N16 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
LCD driver
(1) When Page 0 is selected for the display memory, the memory data and the display will not match
until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the
display memory by executing initial processing.
(2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data
cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB).
Clock timer
(1) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Conse-
quently, perform flag read-out (reset the flag) as necessary at reset.
(2) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer
may be counted up at timer reset.
Stopwatch timer
If timer data is read out in the RUN status, the timer must be made into the STOP status, and after
data is read out the RUN status can be restored. If data is read out when a carry occurs, the data
cannot be read correctly.
Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4
cycle).
Sound generator
A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output
registers (R10, R13) and the buzzer frequency selection registers (BZFQ0–BZFQ2) changes.
Event counter
(1) After the event counter has written data to the EVRUN register, it operates or stops in synchroniza-
tion with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the
above timing when input signals (input to K02 and K03) are being received.
(2) To prevent erroneous reading of the event counter data, read out the counter data several times,
compare it, and use the matching data as the result.
Analog comparator
(1) To reduce current consumption, set the analog comparator to OFF when it is not necessary.
(2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to
stabilize before reading the output data of the analog comparator from AMPDT.
Supply voltage detection (SVD) circuit
(1) The SVD circuit takes 100 sec from the time it goes ON until a stable result is obtained. For this
reason, keep the following software notes in mind:
After writing "1" on SVDON, write "0" after at least 100 sec has elapsed (possible with the next
instruction when the OSC1 clock is used as the CPU clock) and then read the SVDDT.
(2) SVDON resides in the same bit at the same address as SVDDT, and one or the other is selected by
write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth)
cannot be used for SVDON control.
Heavy load protection function (S1C60A16)
(1) More current is consumed in the heavy load protection mode than in the normal mode. Unless it is
necessary, be careful not to set the heavy load protection mode with the software.
(2) The heavy load protection function is available only in the S1C60A16.
The S1C60N16 and S1C60L16 do not support this function and HLMOD can be used as a general-
purpose R/W register that does not affect IC's operations.
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