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參數(shù)資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數(shù)： | 48/105頁 |
| 文件大?。?/td> | 841K |
| 代理商： | S1C60L16F0A0100 |
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S1C60N16 TECHNICAL MANUAL
EPSON
37
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SCS1, SCS0: Clock mode selection register (2F2HD3, D2)
Selects the synchronous clock for the serial interface (SCLK).
Table 4.7.5.2 Synchronous clock selection
SCS1
0
1
SCS0
0
1
0
1
Mode
Master mode
Slave mode
Synchronous clock
CLK
CLK/2
CLK/4
External clock
CLK: CPU system clock
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
At initial reset, external clock is selected.
SE2: Clock edge selection register (2F2HD1)
Selects the timing for reading in the serial data input.
When "1" is written : Rising edge of SCLK
When "0" is written : Falling edge of SCLK
Read-out : Valid
Selects whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge (at "1"
writing) or falling edge (at "0" writing) of the SCLK signal.
Pay attention if the synchronous clock goes into reverse phase (SCLK
→ SCLK) through the mask option.
SCLK rising = SCLK falling,
SCLK falling = SCLK rising
When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous
clock (SCLK) when data is written to register SE2.
The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising
edge.
At initial reset, falling edge of SCLK (SE2 = "0") is selected.
EISIO: Interrupt mask register (2F2HD0)
This is the interrupt mask register of the serial interface.
When "1" is written : Enabled
When "0" is written : Masked
Read-out : Valid
At initial reset, this register is set to "0" (mask).
ISIO: Interrupt factor flag (2F3HD0)
This is the interrupt factor flag of the serial interface.
When "1" is read out : Interrupt has occurred
When "0" is read out : Interrupt has not occurred
Writing : Invalid
From the status of this flag, the software can decide whether the serial interface interrupt.
The interrupt factor flag is reset when it has been read out.
Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/
output.
Be sure that the interrupt factor flag reading is done with the interrupt in the DI status (interrupt flag =
"0").
At initial reset, this flag is set to "0".
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