- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C60L05F 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C60L05F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 |
| 封裝： | PLASTIC, QFP6-60 |
| 文件頁數(shù)： | 71/104頁 |
| 文件大?。?/td> | 697K |
| 代理商： | S1C60L05F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當(dāng)前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁
S1C60N05 TECHNICAL MANUAL
EPSON
61
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when "1" is written to them, and masked (interrupt
disabled) when "0" is written to them. After an initial reset,
the interrupt mask register is set to "0".
Table 4.10.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Specific masks and
factor flags for inter-
rupt
Table 4.10.2
Interrupt mask registers and
interrupt factor flags
Interrupt mask register
Interrupt factor flag
(0EBH D2)
(0EBH D1)
(0EBH D0)
(0ECH D0)
(0E8H D3)
(0E8H D2)
(0E8H D1)
(0E8H D0)
IT2
IT8
IT32
IAD
(0EFH D2)
(0EFH D1)
(0EFH D0)
(0F0H D0)
IK0
(0EDH D0)
EIT2
EIT8
EIT32
EIAD
EIK03*
EIK02*
EIK01*
EIK00*
*
There is an interrupt mask register for each input port pin.
When an interrupt request is input to the CPU, the CPU
begins interrupt processing. After the program being exe-
cuted is suspended, interrupt processing is executed in the
following order:
The address data (value of the program counter) of the
program step to be executed next is saved on the stack
(RAM).
The interrupt request causes the value of the interrupt
vector (page 1, 01H–07H) to be loaded into the program
counter.
The program at the specified address is executed (execu-
tion of interrupt processing routine).
The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
Interrupt vectors
Note
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C60L05D | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC53 |
| S1C60L13F | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| S1C60L13D | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC79 |
| S1C60A13F | 4-BIT, MROM, 1.2 MHz, MICROCONTROLLER, PQFP80 |
| S1C60L16F0A0100 | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C60L08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60L16 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N05 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N16 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。