參數(shù)資料
型號(hào)： S1C60L05F
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60
封裝： PLASTIC, QFP6-60
文件頁(yè)數(shù)： 52/104頁(yè)
文件大?。?/td> 697K
代理商： S1C60L05F
S1C60N05 TECHNICAL MANUAL
EPSON
43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Table 4.7.1 shows the clock timer control bits and their
addresses.
Control of clock
timer
Table 4.7.1 Control bits of clock timer
Timer data (0E3H)
The l6 Hz to 2 Hz timer data of the clock timer can be read
from this register. These four bits are read-only, and write
operations are invalid.
After an initial reset, the timer data is initialized to "0H".
Interrupt mask registers (0EBH D0–D2)
These registers are used to mask the clock timer interrupt.
When "1" is written:
Enabled
When "0" is written:
Masked
Reading:
Valid
The interrupt mask register bits (EIT32, EIT8, EIT2) mask
the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).
After an initial reset, these registers are all set to "0".
TM0–TM3
EIT32, EIT8, EIT2
*
1 Initial value following initial reset
*
2 Not set in the circuit
*
3 Undefined
*
4 Reset (0) immediately after being read
*
5 Always "0" when being read
*
6 Refer to main manual
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
0E3H
TM0
R
TM3
TM2
TM1
TM0
–
Clock timer data 2 Hz
Clock timer data 4 Hz
Clock timer data 8 Hz
Clock timer data 16 Hz
High
Low
TM1
TM2
TM3
*3
0EBH
EIT32
0
EIT2
EIT8
EIT32
0
Interrupt mask register (clock timer) 2 Hz
Interrupt mask register (clock timer) 8 Hz
Interrupt mask register (clock timer) 32 Hz
Enable
Mask
EIT8
R/W
EIT2
0
R
*5
0EFH
IT32
R
0
IT2
IT8
IT32
0
Interrupt factor flag (clock timer) 2 Hz
Interrupt factor flag (clock timer) 8 Hz
Interrupt factor flag (clock timer) 32 Hz
Yes
No
IT8
IT2
0
*5
*4
0F9H
TMRST
W
0
TMRST
Reset
Clock timer reset
Reset
–
0
R
0
*5
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