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參數(shù)資料
| 型號： | RTL8316 |
| 英文描述： | Specifications |
| 中文描述： | 規(guī)格 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 375K |
| 代理商： | RTL8316 |
RTL8316
2001/11/09
Rev.1.72
11
6. Functional Description
6.1 Reset
After hardware reset, the RTL8316 will determine some default settings through the hardware strap pins and then write
abilities to connected PHY management registers via MDC/MDIO. It is most important that the RTL8316 and connected
PHYs use the same reset signal source. Otherwise, if the reset action of PHY is finished after the RTL8316, there is no
guarantee of proper operation on the expected port speed, duplex and flow control ability.
6.2 RMII interface
The RTL8316 provides a 10/100 Mbps low pin count RMII interface to connect with PHYs. The RMII is capable of supporting
10Mbps and 100Mbps data rates. A single clock reference, 50MHz, sourced from an external clock input, is used for receive
and transmit. It also provides independent 2 bit wide (di-bit) transmit and receive data paths. As the REFCLK is 10 times the
data rate in 10Mbps mode each data di-bit must be output on TXD[1:0] and input on RXD[1:0] for ten consecutive REFCLK
cycles. The RTL8316 can regenerate the COL signal of the MII internally by ANDing TXEN and CRS as recovered from
CRSDV. Note that TXEN cannot be ANDed directly with CRSDV since CRSDV may toggle at the end of the frame to provide
separation of RXDV and CRS.
RMII Specification Signals are as below,
Signal Name
Direction
(with respect
to the PHY)
Input
Direction
(with respect
to the RTL8316)
Input
Description
REFCLK
Synchronous clock reference for receive, transmit and
control interface.
Carrier Sense/Receive Data Valid
Receive Date
Transmit Enable
Transmit Data
CRSDV
RXD[1:0]
TXEN
TXD[1:0]
Output
Output
Input
Input
Input
Input
Output
Output
6.3 Serial Management Interface MDC/MDIO
The RTL8316 supports PHY management through the serial MDIO and MDC signal lines (SMI). After power on reset, the
RTL8316 write abilities to the advertisement register 4 of connected PHY and restarts the auto-negotiation process through
MDIO using PHY, addressed incrementally from 10000b (16) to 11111b (31). After restarting auto-negotiation, the RTL8316
will continuously read the link status and link partner's ability which includes speed, duplex and flow control of the PHY
devices via MDIO.
When the RST# pin is asserted low, the MDC and MDIO pins are both in a tri-state. This feature provides the ability for an
external controller to access PHY's internal registers easily by using the same serial management interface during the period of
RST# active low. When RST# is active high, the MDC changes to be an output pin and MDIO becomes an I/O pin.
Following is the SMI management frame format:
Management frame fields
PRE
ST
OP
PHYAD
REGAD
READ
1…1
01
10
AAAAA
RRRRR
WRITE
1…1
01
01
AAAAA
RRRRR
IDLE
Z
Z
TA
Z0
10
DATA
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
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