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參數(shù)資料
| 型號(hào)： | RTL8139C_PLUS |
| 英文描述： | RTL8139C_Plus Specification |
| 中文描述： | RTL8139C_Plus規(guī)范 |
| 文件頁(yè)數(shù)： | 21/58頁(yè) |
| 文件大?。?/td> | 616K |
| 代理商： | RTL8139C_PLUS |
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RTL8100B(L)
2001-11-9
Rev.1.41
21
5.12 Media Status Register
(Offset 0058h, R/W)
This register allows configuration of device and PHY options, and provides PHY status information.
Bit
7
R/W
R/W
Symbol
TXFCE/
LdTXFCE
Description
Tx Flow Control Enable:
The flow control is valid in full-duplex
mode only. This register’s default value comes from 93C46.
RTL8100B(L)
ANE = 1
ANE = 1
ANE = 1
ANE = 0 &
full-duplex mode
ANE = 0 &
half-duplex mode
Remote
TXFCE/LdTXFCE
R/O
R/W
R/W
R/W
NWAY FLY mode
NWAY mode only
No NWAY
-
-
invalid
NWAY FLY mode : NWAY with flow control capability
NWAY mode only : NWAY without flow control capability
RX Flow control Enable:
The flow control is enabled in full-duplex
mode only. The default value comes from 93C46.
Reserved
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
Speed:
Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
Inverse of Link status. 0 = Link OK. 1 = Link Fail.
Set, when RTL8100B(L) sends pause packet. Reset, when
RTL8100B(L) sends timer done packet.
Pause Flag:
Set, when RTL8100B(L) is in backoff state because a
pause packet received. Reset, when pause state is clear.
6
R/W
RXFCE
5
4
-
R
-
Aux_Status
3
R
SPEED_10
2
1
R
R
LINKB
TXPF
0
R
RXPF
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