參數(shù)資料
型號: RT9210GS
廠商: Richtek Technology Corporation
英文描述: Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination
中文描述: 雙5V的同步降壓型DC - DC PWM控制器,用于DDR內(nèi)存VDDQ和VTT終端
文件頁數(shù): 3/17頁
文件大?。?/td> 360K
代理商: RT9210GS
RT9210
Preliminary
DS9210-05 March 2007
3
www.richtek.com
Functional Pin Description
UGATE1 (Pin 1)
V
DDQ
upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT1 (Pin 2)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT1 pin and the
PHASE1 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
PHASE1 (Pin 3)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. PHASE1 is used to
monitor the voltage drop across the upper MOSFET of
the V
DDQ
regulator for over-current protection.
VREF (Pin 4)
Buffered internal reference voltage of V
DDQ
/ 2. This output
should be used to provide the reference voltage for the
Northbridge chipset and DDR memory.
FB1 (Pin 5)
V
DDQ
feedback voltage. This pin is the inverting input of
the error amplifier. FB1 senses the V
DDQ
through an
external resistor divider network.
COMP1 (Pin 6)
V
DDQ
external compensation. This pin internally connects
to the output of the error amplifier and input of the PWM
comparator. Use a RC + C network at this pin to
compensate the feedback loop to provide optimum
transient response.
SENSE1 (Pin 7)
This pin is connected directly to the regulated output of
V
DDQ
supply. This pin is also used as an input to create
the voltage at V
REF.
VREF_IN (Pin 8)
This pin is used as an option to overdrive the internal
resistor divider network that sets the voltage for both V
REF
and the reference voltage for the V
TT
supply. A 100pF
capacitor between VREF_IN and ground is recommended
for proper operation.
GNDA (Pin 9)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Ties the pin directly to ground
plane with the lowest impedance.
BOOT2 (Pin 11)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT2 pin and the
PHASE2 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
UGATE2 (Pin 12)
V
TT
upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
PGND2 (Pin 13)
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
LGATE2 (Pin 14)
V
TT
lower gate driver output. Connect to gate of the low-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
VCC (Pin 15)
Connect this pin to a well-decoupled 5V bias supply. It is
also the positive supply for the lower gate driver, LGATE2.
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