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參數(shù)資料
| 型號(hào)： | RT9210GS |
| 廠商： | Richtek Technology Corporation |
| 英文描述： | Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination |
| 中文描述： | 雙5V的同步降壓型DC - DC PWM控制器，用于DDR內(nèi)存VDDQ和VTT終端 |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 360K |
| 代理商： | RT9210GS |
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RT9210
Preliminary
DS9210-05 March 2007
15
www.richtek.com
Layout Consideration
The layout is very important when designing high frequency
switching converters. Layout will affect noise pickup and
can cause a good design to perform with less than
expected results.
1. Even though double-sided PCB is usually sufficient for
a good layout, four-layer PCB is the optimum approach to
reducing the noise. Use the two internal layers as the
power and GND planes, the top layer for power connections
with wide, copper filled areas, and the bottom layer for the
noise sensitive traces.
2. There are two sets of critical components in a DC-DC
converter. The switching components are the most critical
because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. The
others are the small signal components that connect to
sensitive nodes or supply critical bypass current and signal
coupling. Make all critical component ground connections
with vias to GN
D plane.
10 100 1k 10k 100k 1M
Frequency (Hz)
-40
0
40
80
-60
80
40
0
20
60
-20
-40
-60
Loop Gain
Compensation
Gain
Modulator
Gain
G
3. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces with
heavy copper to keep the parasitic resistance low. Place
the output capacitors as close to the load as possible.
4. The inductor, output capacitor and the MOSFET should
be as close to each other as possible. This helps to reduce
the EMI radiated.
5. Place the switching MOSFET as close to the input
capacitors as possible. The MOSFET gate traces to the
IC must be as short, straight, and wide as possible. Use
copper filled polygons on the top and bottom layers for
the PHASE nodes.
6. Place the C
BOOT
as close as possible to the BOOT and
PHASE pins.
7. The feedback part of the system should be kept away
from the inductor and other noise sources, and be placed
close to the IC. Connect to the GND pin with a single
trace, and connect this local GND trace to the output
capacitor GND.
8. Minimize the leakage current paths on the OCSET/SD
pin and locate the resistor as close to the OCSET/SD pin
as possible because the internal current source isonly
40
μ
A.
9. In multilayer PCB, use one layer as ground plane and
have a control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current path to a separate loop that does not interfere
with the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point.
High crossover frequency is desirable for fast transient
response, but often jeopardize the system stability. In
order to cancel one of the LC filter poles, place the zero
before the LC filter resonant frequency. In the experience,
place the zero at 75% LC filter resonant
frequency.Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching frequency.
The second pole be place at half the switching frequency.
Figure 3
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