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參數(shù)資料
RT9210
Preliminary
DS9210-05 March 2007
14
www.richtek.com
The output LC filter introduces a double pole,
40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The Resonant
frequency of the LC filter expressed as follows :
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
C
and Z
F
as Figure 2 shows.
Modulator Frequency Equations
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This transfer function is dominated
by a DC gain and the output filter (L
O
and C
O
), with a
double pole
frequency at F
LC
and a zero at F
ESR
. The DC gain of the
modulator is the input voltage (V
IN
) divided by the peak-
to-peak oscillator voltage V
RAMP
.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
Figure 3 shows the DC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
Z
C
and Z
F
to provide a stable, high bandwidth loop.
+
-
Zc
Zf
VREF
+
-
Lo
VRAMP
PWM
Co
ESR
Vin
Compensator
PWM
Comparator
Vout
C2
C1
R2
R1
COMP1
VREF
EA
+
-
FB1
RT9210
V
OUT
Zc
Zf
Rf
O
O
P(LC)
F
C
L
2
1
×
×
=
π
ESR
C
2
1
F
O
Z(ESR)
×
×
=
π
Feedback Compensation
The RT9210 is a voltage mode controller; the control loop
is a single voltage feedback path including an error amplifier
and PWM comparator as Figure 1 shows. In order to
achieve fast transient response and accurate output
regulation, a adequate compensator design is necessary.
The goal of the compensation network is to provide
adequate phase margin (greater than 45 degrees) and the
highest 0dB crossing frequency. And to manipulate loop
frequency response that its gain crosses over 0dB at a
slope of -20dB/dec.
Figure 1
Figure 2
)
C
//
(C
R
2
1
F
C
R
2
1
F
0
F
2
P1
2
2
Z1
P1
×
=
×
×
=
=
π
π
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| RT9210GS | 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination |
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| RT9210PS | 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:Dual 5V Synchronous Buck DC-DC PWM Controller for DDR Memory VDDQ and VTT Termination |
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| RT9212GC | 制造商:RICHTEK 制造商全稱:Richtek Technology Corporation 功能描述:Dual 5V Synchronous Buck PWM DC-DC and Linear Power Controller |
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