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參數(shù)資料
| 型號： | RD74LVC273BTELL |
| 元件分類： | 鎖存器 |
| 英文描述： | LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 81K |
| 代理商： | RD74LVC273BTELL |
Rev.1.00 Jun. 16, 2004 page 1 of 8
RD74LVC273B
Octal D-type Flip-Flops with Clear
REJ03D0323–0100Z
Rev.1.00
Jun. 16, 2004
Description
The RD74LVC273B has eight edge trigger D-type flip-flops with clear in a 20-pin package. Data on the D input having
the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The
clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-
powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
V
CC = 1.65 V to 5.5 V
All inputs V
IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs V
OUT (Max.) = 5.5 V (@VCC = 0 V)
Typical V
OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical V
OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High Output current ±4 mA (@V
CC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±12 mA (@VCC = 2.7 V)
±24 mA (@VCC = 3.0 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
RD74LVC273BFPEL
SOP–20 pin(JEITA)
FP–20DAV
FP
EL (2,000 pcs / reel)
RD74LVC273BTELL
TSSOP–20 pin
TTP–20DAV
T
ELL (2,000 pcs / reel)
Function Table
Inputs
CLR
CLK
D
Output Q
LX
X
L
H
↑
HH
H
↑
LL
H
↓
XQ0
Note:
H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Q0:
Output level before the indicated steady state input conditions were established.
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