參數(shù)資料
型號(hào): RD28F3204W30B70
廠商: INTEL CORP
元件分類: 存儲(chǔ)器
英文描述: 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA80
封裝: 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù): 81/82頁(yè)
文件大小: 749K
代理商: RD28F3204W30B70
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
75
Partition Region 2 Information
(1)
See table below
Address
Len
Bot
2
68:
69:
1
6A:
P = 39h
Description
Bottom
(P+2F)h
(P+30)h
(P+31)h
Top
(P+27)h Number of identical partitions within the partition region
(P+28)h
(P+29)h
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Read mode
bits 0
3 = number of simultaneous Program operations
bits 4
7 = number of simultaneous Erase operations
(Optional flash features and commands)
Top
60:
61:
62:
(P+32)h
(P+2A)h
1
6B:
63:
(P+33)h
(P+2B)h
1
6C:
64:
(P+34)h
(P+2C)h
1
6D:
65:
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
(P+3A)h
(P+3B)h
(P+2D)h Partition Region 2 Erase Block Region 1 Information
(P+2E)h
bits 0
15 = y, y+1 = number of identical-size erase blocks
(P+2F)h
bits 16
31 = z, region erase block(s) size are z x 256 bytes
(P+30)h
(P+31)h Partition 2 (Erase Region 1)
(P+32)h Minimum block erase cycles x 1000
(P+33)h
Partition 2 (Erase Region 1) bits per cell
bits 0
3 = bits per cell in erase region
bit 4 = reserved for
internal ECC used
(1=yes, 0=no)
bits 5
7 = reserve for future use
Partition 2 (erase region 1) pagemode and synchronous mode
capabilities as defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
4
6E:
6F:
70:
71:
72:
73:
74:
66:
67:
68:
69:
6A:
6B:
6C:
2
1
(P+3C)h
(P+34)h
1
75:
6D:
(P+35)h Partition Region 2 Erase Block Region 2 Information
(P+36)h
bits 0
15 = y, y+1 = number of identical-size erase blocks
(P+37)h
bits 16
31 = z, region erase block(s) size are z x 256 bytes
(P+38)h
(top parameter device only)
(P+39)h Partition 2 (Erase Region 2) minimum block erase cycles x 1000
(P+3A)h (top parameter device only)
(P+3B)h
Partition 2 (Erase Region 2) bits per cell (top parameter only)
bits 0
3 = bits per cell in erase region
bit 4 = reserved for
internal ECC used
(1=yes, 0=no)
bits 5
7 = reserve for future use
Partition 2 (Erase Region 2) pagemode and synchronous mode
capabilities as defined in Table 10. (top parameter only)
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
4
6E:
6F:
70:
71:
72:
73:
74:
2
1
(P+3C)h
1
75:
(P+3D)h
(P+3E)h
(P+3D)h Features Space definitions (Reserved for future use)
(P+3E)h Reserved for future use
TBD
Resv'd
76:
77:
76:
77:
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0
3 = number of simultaneous Program operations
bits 4
7 = number of simultaneous Erase operations
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0
3 = number of simultaneous Program operations
bits 4
7 = number of simultaneous Erase operations
Partitions' erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in
bulk
x = number of erase block regions w/ contiguous same-size
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