
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
46
Order Number: 314749-05
10.0
Command Definitions
Table 24 shows valid device command codes and descriptions.
Table 24: Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Description
Read
0xFF
Read Array
Places the device in Read Array mode. Array data is output on DQ[15:0].
0x70
Read Status
Register
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. SR data is output on DQ[7:0].
0x90
Read Device ID
or Configuration
Register
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or Protection Register data on DQ[15:0].
0x98
Read Query
Places the device in Read Query mode. Subsequent reads output Common
Flash Interface information on DQ[7:0].
0x50
Clear Status
Register
The WSM can only set SR error bits. The Clear Status Register command is
used to clear the SR error bits.
Write
0x40
Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the SR Data for synchronous Non-array reads. The Read Array
command must be issued to read array data after programming has finished.
Write
0x10
Alternate Word
Program Setup
Equivalent to the Word Program Setup command, 0x40.
0xE8
Buffered Program
This command loads a variable number of words up to the buffer size of 32
words onto the program buffer.
0xD0
Buffered Program
Confirm
The confirm command is Issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
0x80
BEFP Setup
First cycle of a 2-cycle command; initiates the BEFP mode. The CUI then
waits for the BEFP Confirm command, 0xD0, that initiates the BEFP
algorithm. All other commands are ignored when BEFP mode begins.
0xD0
BEFP Confirm
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
Erase
0x20
Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR [5,4], and places the
device in Read Status Register mode.
0xD0
Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
SR Data for synchronous Non-array reads.
Suspend
0xB0
Program or Erase
Suspend
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR 2 (program
suspended) or SR 6 (erase suspended), along with SR 7 (ready). The WSM
remains in the suspend mode regardless of control signal states (except for
RST# asserted).
0xD0
Suspend Resume
This command issued to any device address resumes the suspended program
or block-erase operation.