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參數(shù)資料
| 型號(hào)： | QLX4600SIQSR |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC EQUALIZER REC 6.25GBPS 46QFN |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | QLx™ |
| 應(yīng)用： | 銅電纜模塊 |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
13
FN6979.1
November 19, 2009
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx4600-S30 contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification
during active data transmission. Line silence is detected
by measuring the amplitude of the equalized signal and
comparing that to a threshold set by the current at the
DT pin. When the amplitude falls below the threshold,
the output driver stages are muted and held at their
nominal common mode voltage1.
Input Impedance Select
The input impedance of a channel on the QLx4600-S30 is
set high (>200k) when powered down or when IS[k] pin
is pulled low. This provides compatibility with the
Fundamental Reset signal and receiver detection/link
initialization in the PCI Express protocol.
Channel Power-Down
In addition to controlling the input impedance, the IS[k]
pin powers down the equalizer channel when pulled low.
This feature allows a system controller individually to
power down unused channels and to minimize power
consumption. Example: the signal to power down a
channel could come from an Intelligent Platform
Management controller in ATCA applications for
E-Keying. The current draw for a channel is reduced from
50mA to 3.8mA when powered down.
Applications Information
Several aspects of the QLx4600-S30 are capable of being
dynamically managed by a system controller to provide
maximum flexibility and optimum performance. These
functions are controlled by interfacing to the highlighted
pins in Figure 26. The specific procedures for controlling
these aspects of the QLx4600-S30 are the focus of this
section.
Equalization Boost Level
Channel equalization for the QLx4600-S30 can be
individually set to either (a) one of 18 levels through the
DC voltages on external control pins or (b) one of 32
levels via a set of registers programmed by a low speed
serial bus. The pins used to control the boost level are
highlighted in Figure 24. Descriptions of these pins are
listed in Table 1. Please refer to “Pin Descriptions” on
page 3 for descriptions of all other pins on the
QLx4600-S30.
FIGURE 24. CML INPUT EQUIVALENT CIRCUIT FOR THE
QLx4600-S30
FIGURE 25. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx4600-S30
NOTE: The load value of 52Ω is used to internally match
SDD22 for a characteristic impedance of 50Ω.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
IN[k] P
IN[k] N
Buffer
VDD
50
VDD
52
OUT[k] P
OUT[k] N
FIGURE 26. PIN DIAGRAM HIGHLIGHTING PINS USED
FOR DYNAMIC CONTROL OF THE QLx4600-S30
DT
IN1[P]
IN1[N]
VDD
IN2[P]
IN2[N]
VDD
CLK
EN
B
CP
1[A]
CP
1[B]
CP
1[C]
CP
2[B]
CP
2[A]
1
2
3
4
5
6
7
46 45 44
43 42
41 40
8
9
10
11
12
13
14
15
39
16 17 18
19 20
21 22 23
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
IN3[P]
IN3[N]
VDD
IN4[P]
IN43[N]
IS1
IS2
GND
BGREF
OUT1[P]
OUT1[N]
VDD
OUT2[P]
OUT2[N]
VDD
OUT3[P]
OUT3[N]
VDD
OUT4[P]
OUT4[N]
IS3
IS4
MODE
CP
2[C]
EXPOSED PAD
CP
3[C]
CP
4[B]
DO
CP
3[A]
DI
CP
3[B]
CP
4[A]
CP
4[C]
(GND)
QLx4600-S30
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